參數(shù)資料
型號: MAX1002CAX+T
廠商: Maxim Integrated Products
文件頁數(shù): 12/12頁
文件大?。?/td> 0K
描述: IC ADC 6BIT 60MSPS DUAL 36-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
位數(shù): 6
采樣率(每秒): 60M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 941mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
Output Data Format
The conversion results are output on a dual 6-bit-wide
data bus. Data is latched into the ADC output latch fol-
lowing a pipeline delay of one clock cycle (Figure 8).
Output data is clocked out of the respective ADC’s data-
output pins (D_0 through D_5) on the rising edge of the
clock output (DCLK), with a DCLK-to-data propagation
delay (tPD) of 7.1ns. The MAX1002 outputs are TTL com-
patible.
Transfer Function
Figure 9 shows the MAX1002’s nominal transfer function.
Output coding is offset binary with 1LSB = FSR / 63.
MAX1002
Low-Power, 60Msps, Dual, 6-Bit ADC
_______________________________________________________________________________________
9
Figure 9. Ideal Transfer Function
111111
OUTPUT
CODE
111110
111101
100001
100000
011111
011110
000011
000010
000001
000000
-FSR
2
0
1LSB
INPUT VOLTAGE
FSR
2
(_IN+ to _IN-)
Figure 8. MAX1002 Timing Diagram
DATA OUT
1.4V
DATA VALID N - 1
DATA VALID N
1.4V
50%
tSKEW
tDCLK
tAP
tPD
TNK+
(INPUT CLOCK)
DCLK
ANALOG
INPUT
N
N + 1
N + 2
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