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參數(shù)資料
| 型號(hào)： | MAQ28155CXXXX |
| 廠商： | DYNEX SEMICONDUCTOR LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 24 I/O, PIA-GENERAL PURPOSE, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 254K |
| 代理商： | MAQ28155CXXXX |
MA28155
7/20
Input Control Signal Definition (Mode 1)
STBN (Strobe Input).
A low on this input loads data into the input latch.
IBF (Input Buffer Full Register Bit).
A high on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgement.
IBF is set by a STBN active pulse (which strobes data into
the device), and is reset by the rising edge of DSN (which
reads the latched data out of the device).
INTR (Interrupt Request).
A high on this output can be used to interrupt the CPU
when an input device is requesting service, INTR is set by the
STBN being high and IBF being high and INTE being enabled,
It is reset by the falling edge of DSN, This procedure allows an
input device to request service from the CPU by simply
strobing its data into the port,
INTE A: Controlled by bit set/reset of PC4
INTE B: Controlled by bit set/reset of PC2
Figure 9: Strobed Input (PORT A)
Figure 10: Strobed Input (PORT B)
DSN
RD/WN
STBAN
STBBN
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