參數(shù)資料
型號(hào)： MACH11SP
廠商： Electronic Theatre Controls, Inc.
英文描述： High-Performance EE CMOS In-System Programmable Logic
中文描述： 高性能電子工程的CMOS在系統(tǒng)可編程邏輯
文件頁(yè)數(shù)： 1/33頁(yè)
文件大?。?/td> 193K
代理商： MACH11SP
FINAL
Publication#
20405
Amendment/
0
Rev:
C
Issue Date:
August 1997
1
M
MACH 1 & 2 FAMILIES
1
COM’L: -7/10/12/15
IND: -10/12/14/18
MACH211SP-7/10/12/15
High-Performance EE CMOS
In-System Programmable Logic
DISTINCTIVE CHARACTERISTICS
N
JTAG-Compatible, 5-V in-system programming
44 Pins in PLCC and TQFP
64 Macrocells
7.5 ns t
PD
Commercial, 10 ns t
PD
133 MHz f
CNT
32 I/Os; 2 dedicated inputs/clocks
64 Flip-flops; 2 clock choices
4 “PALCE26V16” blocks with buried macrocells
Speed Locking for guaranteed fixed timing
Bus-Friendly Inputs and I/Os
Peripheral Component Interconnect (PCI) compliant (-7/-10/-12)
Programmable power-down mode
N
N
N
Industrial
N
N
N
N
N
N
N
N
IN-SYSTEM PROGRAMMING
In-system programming allows the MACH211SP to be programmed while soldered onto a system
board. Programming the MACH211SP in-system yields numerous benefits at all stages of
development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t
needed, multiple handling steps and the resulting bent leads are eliminated. The design can be
modified in-system for design changes and debugging while prototyping, programming boards in
production, and field upgrades.
The MACH211SP offers advantages with in-system programming. MACH
devices have
extensive routing resources for pin-out retention; design changes resulting in pin-out changes
for many non-Vantis CPLDs cancel the advantages of in-system programming. The MACH211SP
can be deployed in any JTAG (IEEE 1149.1) compliant chain.
GENERAL DESCRIPTION
The MACH211SP is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This
device has approximately six times the logic macrocell capability of the popular PALCE22V10
without loss of speed.
The MACH211SP consists of four PAL
blocks interconnected by a programmable switch matrix.
The four PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays
and programmable macrocells, which can be programmed as high speed or low power, and buried
macrocells. The switch matrix connects the PAL blocks to each other and to all input pins,
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