參數(shù)資料
型號(hào)： MAC7142CPV50
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP100
封裝： LQFP-100
文件頁(yè)數(shù)： 8/60頁(yè)
文件大?。?/td> 760K
代理商： MAC7142CPV50
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.1.1
Preliminary
Electrical Characteristics
Freescale Semiconductor
16
Figure 3. Basic PLL Functional Diagram
The procedure described below can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table 20. First, the VCO Gain at the desired VCO output frequency is
approximated by:
Eqn. 8
The phase detector relationship is given by:
Eqn. 9
ich is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner’s stability
criteria by at least a factor of 10, a typical value for the stability factor is 50.
ζ = 0.9 ensures a good transient
response.
Eqn. 10
And finally the frequency relationship is defined as:
Eqn. 11
With the above inputs the resistance can be calculated as:
Eqn. 12
The capacitance CS can now be calculated as:
Eqn. 13
The capacitance CP should be chosen in the range of:
Eqn. 14
The stabilization delays shown in Table 20 are dependant on PLL operational settings and external
component selection (for example, the crystal and XFC filter).
Phase
Detector
1
REFDV+1
K
φ
fREF
VDDPLL
R
CP
CS
KV
Loop Divider
1
SYNR+1
fVCO
fOSC
1
2
fCMP
VCO
K
V
K
1
e
f1 fVCO
–
()
K
1
1V
--------------------------
=
KΦ
i
ch
–
K
V
=
fC
2
ζ f
REF
πζ
1
ζ
2
+
()
----------------------------------------
1
10
------
fC
fREF
410
--------------
ζ
0.9
=
()
;
<
→
<
n
fVCO
fREF
----------
2
SYNR
1
+
()
==
R
2
π n f
C
KΦ
----------------------------
=
C
S
2
ζ
2
π f
C
R
---------------------
0.516
fC R
-------------
ζ
0.9
=
()
;
≈
=
C
S
20
÷
C
P
C
S
10
÷
≤≤
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