
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
21
3.9.1
Read and Write Bus Cycles
Table 25 lists processor bus output timings. Read/write bus timings listed in
Table 25 are shown in
Table 25. External Bus Output Timing Specifications 1
NOTES:
1. Assumes CLKOUT, CSn, BSn, OE, AS, ADDR[21:0] and DATA[15:0] are configured for full drive strength (via the PIM).
Num
C
Rating
Symbol
Min
Max
Unit
Control Outputs
M6a
P CLKOUT high 2 to chip selects (CS[2:0]) valid
2. The CSn, BSn, OE and AS signals are synchronous to the falling edge of CLKOUT. Therefore, changes on these
signals are triggered by the falling edge of CLKOUT, even though they are specified in relation to the rising edge.
tCHCV
—0.5tCYC + 10
ns
M6b
P CLKOUT
high 2 to byte selects (BS[1:0]) valid
tCHBV
—0.5tCYC + 10
ns
M6c
P CLKOUT hig
h 2 to output select (OE) valid
tCHOV
—0.5tCYC + 10
ns
M6d
P CLKOUT
high 2 to address strobe (AS) valid
tCHASV
—0.5tCYC + 10
ns
M7a
P CLKOUT
high 2 to control output (BS[1:0], OE) invalid
tCHCOI
0.5tCYC + 2
—
ns
M7b
P CLKOUT
high 2 to chip selects (CS[2:0]) invalid
tCHCI
0.5tCYC + 2
—
ns
M7c
P CLKOUT hig
h 2 to address strobe (AS) invalid
tCHASI
0.5tCYC + 2
—
ns
Address and Attribute Outputs
M8
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) valid
tCHAV
—10
ns
M9
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) invalid
tCHAI
2—
ns
Data Outputs
M10
P CLKOUT high to data output (DATA[15:0]) valid
tCHDOV
—13
ns
M11
P CLKOUT high to data output (DATA[15:0]) invalid
tCHDOI
2—
ns
M12
D CLKOUT high to data output (DATA[15:0]) high impedance
tCHDOZ
—9
ns
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MAC7131
products
in
208
MAPBGA
packages