參數(shù)資料
型號(hào)： MAC7101MPV50XX
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144
文件頁(yè)數(shù)： 9/56頁(yè)
文件大小： 757K
代理商： MAC7101MPV50XX
ElectricalCharacteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
17
The capacitance CP should be chosen in the range of:
Eqn. 14
The stabilization delays shown in Table 20 are dependant on PLL operational settings and external
component selection (for example, the crystal and XFC filter).
3.8.2.1
Jitter Information
With each transition of the clock fCMP, the deviation from the reference clock fREF is measured and input
voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will
eliminate the effect of PLL jitter to a large extent.
Figure 4. Jitter Definitions
The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for
larger number of clock periods (N). Thus, jitter is defined as:
Eqn. 15
For N
< 100, the following equation is a good fit for the maximum jitter:
Eqn. 16
Figure 5. Maximum Bus Clock Jitter Approximation
C
S
20
÷
C
P
C
S
10
÷
≤≤
0
tMIN1
12
3
N–1
N
tNOM
tMAX1
tMIN(N)
tMAX(N)
JN
()
max 1
t
MAX N
()
Nt
NOM
--------------------
–1
t
MIN N
()
Nt
NOM
--------------------
–
,
=
JN
()
j
1
N
--------
j
2
+
=
01
5
10
20
15
N
J(N)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MAC7131
products
in
208
MAPBGA
packages
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