參數(shù)資料
型號： MAC7101CPV50
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP144
封裝： LQFP-144
文件頁數(shù)： 13/60頁
文件大?。?/td> 760K
代理商： MAC7101CPV50
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.1.1
Preliminary
Electrical Characteristics
Freescale Semiconductor
20
3.9
External Bus Timing
Table 24 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay
with respect to the rising edge of a reference clock. The reference clock is the
CLKOUT output. All other timing relationships can be derived from these values.
Figure 6. General Input Timing Requirements
Table 24. External Bus Input Timing Specifications(1)
NOTES:
1. Assumes CLKOUT is configured for full drive strength (via the PIM CONFIG2_D[RDS] bit).
Num
C
Rating
Symbol
Min
Max
Unit
M1
P CLKOUT period(2)
2. CLKOUT is equal to the system clock, fSYS. If CLKSEL[PLLSEL] is set then fSYS is equal to fVCO (table Table 20,
K3); if it is clear then fSYS is equal to fOSC (table Table 19, J1a or J1b). Throughout this document, tCYC is used to
specify a unit of time equal to 1
÷ CLKOUT (which is equal to t
fsys).
tCYC
20
—
ns
Control Inputs
M2a
P Control input valid to CLKOUT high(3)
3. The TA pin is the only control input on MAC7100 family devices.
tCVCH
13
—
ns
M3a
P CLKOUT high to control inputs invalid(3)
tCHCII
0—
ns
Data Inputs
M4
P Data input (DATA[15:0]) valid to CLKOUT high
tDIVCH
9—
ns
M5
P CLKOUT high to data input (DATA[15:0]) invalid
tCHDII
0—
ns
CLKOUT (50 MHz)
1.5 V
Valid
Invalid
tSETUP
tHOLD
Input Setup & Hold
Input Rise Time
VH = VIH
VL = VIL
tRISE = 1.5 ns
Input Fall Time
VH = VIH
VL = VIL
tFALL = 1.5 ns
CLKOUT
Inputs
1.5 V
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