HMIC
TM
Silicon Beam-Lead PIN Diodes
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for additional data sheets and product information.
2
V1
MA4PBL027
Electrical Specifications at +25 °C
Symbol
C
T
Conditions
0 V, 1 MHz
2
Units
pF
Typ.
0.048
Max.
C
T
-3 V, 1 MHz
2
pF
0.039
C
T
-10 V, 1 MHz
2
pF
0.033
0.040
C
T
-40 V, 1 MHz
2
pF
0.030
0.040
C
T
0 V, 100 MHz
2,4
pF
0.043
C
T
-3 V, 100 MHz
2,4
pF
0.033
C
T
-10V, 100 MHz
2,4
pF
0.031
C
T
-40V, 100 MHz
2,4
pF
0.027
C
T
0 V, 1 GHz
2,4
pF
0.039
C
T
-3 V, 1 GHz
2,4
pF
0.032
C
T
-10 V, 1 GHz
2,4
pF
0.029
C
T
-40 V, 1 GHz
2,4
pF
0.026
R
S
10 mA, 100 MHz
3,4
3.8
R
S
20 mA, 100 MHz
3,4
3.0
R
S
10 mA, 1 GHz
3,4
3.5
R
S
20 mA, 1 GHz
3,4
2.8
V
F
20 mA
V
0.917
1.1
V
R
-10
μ
A
V
110
I
R
-40 V
nA
1.0
I
R
-90 V
uA
-
10.0
T
L
+10 mA / -6 mA
ns
110
2. Total capacitance,
C
T
, is equivalent to the sum of Junction Capacitance ,Cj, and Parasitic Capacitance, Cpar.
3. Series resistance R
S
is equivalent to the total diode resistance : Rs = Rj ( Junction Resistance) + Rc ( Ohmic Resistance)
4. Rs and C
T
are measured on an HP4291A Impedance Analyzer with die mounted in an ODS-186 package with conductive silver epoxy.
NOTES:
Die Handling
All semiconductor chips should be handled with care
to avoid damage or contamination from perspiration
and skin oils. The use of plastic tipped tweezers or
vacuum pickups is strongly recommended for
individual components. Bulk handling should insure
that abrasion and mechanical shock are minimized.
Die Bonding
These devices were designed to be inserted onto
hard or soft substrates. Recommended methods of
attachment include thermocompression bonding, par-
allel-gap welding, and electrically conductive silver epoxy.
See Application Note M541, “Bonding and
Handling Procedures for Chip Diode Devices” for
More Detailed Assembly Instructions.