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參數(shù)資料
| 型號： | MA31750 |
| 廠商： | Dynex Semiconductor Ltd. |
| 英文描述： | High Performance MIL-STD-1750 Microprocessor |
| 中文描述： | 高性能的MIL - STD - 1750微處理器 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大?。?/td> | 436K |
| 代理商： | MA31750 |
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MA31750
4/42
3.1.1. CONFIGURATION REGISTER
The system configuration register allows the MA31750 to
function with a variety of different system designs.
Implemented features such as a BPU should be indicated as
present by setting bits in an externally-implemented 16-bit
latch - see figure 4 for bit assignments. The latch must be
placed in IO space at the address defined by XIO RCW (8410)
shown in the table of XIO commands, Figure 20c. The
processor decodes this command internally and produces a
discrete output signal CONFWN which may be used as the
external register Output Enable control.
3.1.2. BUILT-IN TEST (BIT)
BIT consists of ten subroutines, as outlined in Figure 6. If
all ten subroutines execute successfully, or no BIT is selected
in the configuration word, a BIT pass is flagged (seen
externally as NPU raised high by the initialization routine). If
any part of BIT fails, a corresponding bit identifying the failed
subroutine is set in General Register R0, Fault Bit 13 is set in
the Fault register (FT) and NPU is left in the low state. Figure 6
defines the coding of BIT results in R0. In the event of such a
failure, the resulting processor reset state will be dependent on
where in BIT the error occurred and may not be the same as
that shown in figure 2. A BIT failure indication in FT will set the
level 1 interrupt request bit of the Pending Interrupt (Pl)
register. Since initialisation disables and masks interrupts, this
interrupt request will not be asserted. Any external interrupts or
faults occurring during BIT will be cleared before program
execution begins and will not be serviced.
The processor maintains an internal configuration register
which is updated from the external register during initialisation
and during the execution of a NOP/BPT (No-op/Breakpoint)
instruction. The internal configuration register is used to
control the CPU. Note that although the external register can
be read using XIO RCW, this does not affect the internal
configuration. Note: if the interrupt level/edge trigger select bit
- (bit 4) is changed in the internal register during normal
operation of the device, one or more spurious interrupts may
occur.
When in 1750B mode, the processor needs to know how
many Page Banks are implemented in the external system so
that Status Word changes can be protected properly. MIL-
STD-1750B allows the options 0,1,2,4,8 or 16. The actual
selection should be coded into the three configuration register
bits MMU0, MMU1 and MMU2 as shown in figure 5.
In 1750A mode, setting any of the MMU select bits
indicates the presence of an MMU, the actual code is
unimportant in this mode.
BPU selects bits 2:0 should be set to indicate how much
BPU-protected memory exists on the system. If no BPU is
present, all three bits should be zero.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14-15
Function
MMU Select 0
BPU Select 0
1 = Console operation enabled
MMU Select 1
Interrupt sensitivity (1 = level, 0 = edge)
MMU Select 2
Parity sense (1 = odd, 0 = even)
1= BIT on power-up
1 = Start-Up ROM present
1 = DMA device present
1=1750A mode, 0=1750B mode
1=Instruction set expansion enabled
BPU Select 1
BPU Select 2
Reserved for future expansion
Figure 4: Configuration Word Bits
Selected bit
MMU1
0
0
1
1
0
0
1
Function
MMU2
0
0
0
0
1
1
1
Note:
In 1750A mode, setting any or all of the MMU
select bits indicates the presence of an MMU.
MMU0
0
1
0
1
0
1
X
No MMU in system
1 Page Bank (PB0)
2 Page Banks (PB0-1)
4 Page Banks (PB0-3)
8 Page Banks (PB0-7)
16 Page Banks (PB0-15)
16 Page Banks (PB0-15)
Figure 5: MMU Selection Bits
Test Coverage
Machine
Cycles
47
79
18
5632
Bit set
on fail
7
7
8
9
Temporary Registers (T0-T11)
General Registers (R0-R15)
Flags Block
Sequencer Operation and ROM
checksum
Divide routine Quotient Shift
Network
Multiplier and ALU
Barrel shift Network
Interrupts and fault handling and
detection
Address generator block
Instruction pipeline
Note:
BIT pass is indicated by all zeros
in FT bits 13,14, and 15
12
10
13
13
17
11
12
13
13
15
14
15
Figure 6: Built-In Test Coverage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MA31751 | Memory Management & Block Protection Unit |
| MA31753 | DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA3690 | 1553B Bus Controller/Remote Terminal |
| MA3691 | 1553B Bus Controller/Remote Terminal |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MA31751 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:Memory Management & Block Protection Unit |
| MA31753 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:DMA Controller (DMAC) For An MA31750 System |
| MA31755 | 制造商:DYNEX 制造商全稱:Dynex Semiconductor 功能描述:16-Bit Feedthrough Error Detection & Correction Unit EDAC |
| MA318 | 功能描述:CPU與芯片冷卻器 INTEL P111 FC-PGA RoHS:否 制造商:ADLINK Technology 尺寸: 電壓額定值: 功率額定值: 速度: 氣流: 系列: |
| MA3180 | 制造商:PANASONIC 制造商全稱:Panasonic Semiconductor 功能描述:Silicon planar type |
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