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參數(shù)資料
| 型號： | MA17502 |
| 廠商： | Dynex Semiconductor Ltd. |
| 英文描述： | Radiation Hard MIL-STD-1750A Control Unit |
| 中文描述： | 輻射硬的MIL - STD - 1750A控制單元 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 272K |
| 代理商： | MA17502 |
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MA17502
7/30
Label
Cycle
MAIN
B1
P
B1
1.
2.
3.
Enable Control of DMAE Output signal
-
Clear MAS281 Execution Unit Status Word (SW)
Clear Interrupt Mask (MK) (Internal l/O command, SKM, 2000H)
Clear Pending lnterrupt Register (Pl) and Fault Register (FT) (lnternal l/O Command, CLlR, 2001H)
Clear Instruction Counter (IC)
-
Disable Interrupts (Internal l/O Command, DSBL, 2003H)
-
Clear MMU Status Word (lnternal l/O Command, WSW, 200EH) (Note 1)
-
Disable DMA Access (Internal l/O Command, DMAD, 4007H)
-
Read Configuration Register (Internal l/O Command, RCW, 8400H, CONFWN Drops low per Figure
25, Section 5.0)
-
-
- (If Output Discrete Register Present, then Continue; Else, Skip to 18)
(16). -
(17). Clear Output Discrete Register (External l/O Command)
19.
- (If BPU present, then Branch to BPU; else, continue)
20.
-
21.
- (If MMU present, then Branch to MMU; Else, Continue)
22.
- (Setup Temporary Register to indicate No MMU Present)
23.
- (Branch to MAS281 BIT)
24.
-
25.
Enable Start-Up ROM (Internal l/O Command, ESUR, 4004H; SURE Raises High per Figure 25,
Section 5.0)
26.
-
27.
Clear and Start Timer A (Internal l/O Command, OTA, 400AH)
28.
Reset the Trigger-Go timer (Internal l/O Command, GO, 400BH)
29.
-
30.
Clear and Start Tlmer B (Internal l/O Command, OTB, 400EH)
31.
- (Branch to Load Instruction Pipeline Routine)
32.
Load data-ln register (Dl) and instruction Register A (IA) from [IC], Increment IC
33.
Load Data-ln Register (Dl) and lnstruction Register a (lA) from [lC] ([lA] Moves to lB), lncrement lC
Map Instruction Register B (IB) into Microcode Routine
(1).
-
(2).
- (Set Loop to Clear Memory Protect RAM)
(3).
Clear a Location in MPRAM (Internal l/O Command, LMP, 50XXH), Increment Address; Do 128 Times
(4).
- (Branch Back to 20.)
(1).
-
(2).
-
(3).
- (Setup Loop to Load Instruction Page Registers (IPR) and Operand Page Registers (OPR) wlth
Sequential Values of 0 to 255)
(4).
-
(5).
-
(6).
Load a Location in the IPR with the value of the Locatron Address (Internal l/O Command, WIPR,
51XYH)
(7).
Load a Location in the OPR Increment Loaded Value with the Value of the Location Address (Internal
I/O Command, WOPR, 52XYH)
(8).
- (Increment IPR Address)
(9).
- (Increment OPR Address - Repeat Loop [4. - 9.] 256 Times)
(10). - (Setup Temporary Register to Indicate MMU Present; Branch back to 23)
B1
4.
P
B1
P
B1
P
B1
P
B1
5.
6.
7.
8.
9.
10.
11.
12.
P
P
B2
P
I/O
B2
P
B2
P
B2
P
B1
13.
14.
15.
P
B1
B1
P
B1
B2
M
M
BPU
P
P
I/O
MMU
P
P
P
P
P
I/O
I/O
P
P
B2
Notes:
1. This operation Is performed whether or not an MMU is present.
2. “-” indicates internal CPU operation.
3. Sequence numbers in “( )” are performed only under the stated conditions.
4. Each step enumerated above represents a single machine (SYNC) cycle of the type shown in the “Cycle” column.
“P” indicates a 5 OSC cycle, 60% duty cycle, machine cycle.
“I/O” and “M” indicate a 5 OSC cycle, 50% duty cycle, machine cycle.
“B1” indicates a 6 OSC cycle 50% duty cycle machine cycle.
“B2” indicates a 6 OSC cycle 66% duty cycle machlne cycle.
Table 2: MAS281 Initialisation Sequence
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