參數(shù)資料
型號(hào)： MA17501
廠商： Dynex Semiconductor Ltd.
英文描述： Radiation Hard MIL-STD-1750A Execution unit
中文描述： 輻射硬的MIL - STD - 1750A執(zhí)行單元
文件頁(yè)數(shù)： 8/35頁(yè)
文件大?。?/td> 431K
代理商： MA17501
MA17501
8/35
3.3.5 Instruction/Operand (IN/OPN)
Output/Hi-z. lN/OPN high indicates an instruction is to be
read from memory during the current AD Bus cycle. IN/OPN is
low for all other MAS281 directed AD Bus transfers. The
Memory Management Unit/Block Protection Unit
(MMU(BPU)), when configured as a MMU, uses lN/OPN to
select the proper page register set within the specified page
register group.
IN/OPN is asserted at the SYNCN high-to-low transition
and remains valid for the duration of the current SYNCN
period. lN/OPN is placed in the high-impedance state during
DMA cycles by PAUSEN low and during the Hold state by
HLDAKN low.
3.3.6 Ready (RDYN)
Input. During external AD Bus transfers (those dealing with
devices external to the MAS281 chip set), a low is required on
this input to allow the MAS281 machine cycle to complete
(high-to-low transition of SYNCN). RDYN high is used to
prolong the data portion of the machine cycle (SYNCN high) to
accommodate slow memory and l/O devices. The MAS281
assumes memory or l/O devices are NOT ready to provide
(accept) data to (from) the AD Bus, and requires these devices
to signal their readiness via the RDYN input.
A low on RDYN, enveloping the current machine cycle's
fifth (or later) OSC cycle high-to-low transition, allows the
current machine cycle to complete (SYNCN high-to-low
transition) at the following low-to-high transition of the OSC
input.
3.3.2 Data Strobe (DSN)
Output/Hi-z. DSN low indicates that data is on the AD Bus
(write/output cycles) or that the MAS281 AD Bus drivers are in
the high-impedance state (read/input cycles). For write/output
cycles, the data is guaranteed stable at the low-to-high
transition of DSN. For read/input cycles, the DSN low-to-high
transition indicates the acceptance of data by the MAS281
(SYSCLK1N high-to-low transition latches AD Bus data into
the lA and Dl registers).
DSN is placed in the high-impedance state during DMA
cycles by PAUSEN low and during the Hold state by HLDAKN
low. DSN is held high, for the entire machine cycle, during
internal non-AD Bus operations via microcode.
3.3.3 Read/Write (RD/WN)
Output/Hi-z. RD/WN defines the direction of data flow on
the bidirectional AD Bus and provides read/write cycle
information to the MMU(BPU) for write protection control.
RD/WN high indicates a read/input bus cycle and data transfer
to the MAS281. RD/WN low indicates a write/output bus cycle
and data transfer from the MAS281.
This signal is asserted at the SYNCN high-to-low transition
and remains valid for the duration of the current SYNCN
period. RD/WN is placed in the high impedance state during
DMA cycles by PAUSEN low and during the Hold state by
HLDAKN low.
3.3.4 Memory/lnput-Output (M/ION)
Output/Hi-z. M/lON defines the type of device involved in
the data transfer occurring on the AD Bus and provides
functional control for the lnterrupt Unit (lU) and the Memory
Management Unit/Block Protection Unit (MMU(BPU)). The lU
ignores memory transfer AD Bus activity and the MMU(BPU)
uses M/lON to decide whether to decode the address
information on the AD Bus as an MMU(BPU) XlO command or
a memory address. M/lON high indicates a memory access,
and M/lON low indicates an input-output operation.
This signal is asserted at the SYNCN high-to-low
transition and remains valid for the duration of the current
SYNCN period. M/lON is placed in the high impedance state
during DMA cycles by PAUSEN low and during the Hold state
by HLDAKN low. M/lON is raised high, for the entire machine
cycle, during internal non AD Bus operations via microcode.
3.4 BUSES
The following is a discussion of the communication buses
connecting the MA17501 to the other chips of the MAS281 set.
The AD Bus transfers all data and instructions and the M Bus
provides the microcode instructions from the MA17502.
3.4.1 Address/Data Bus (AD Bus)
Input/Output/Hi-z. These signals comprise a 16-bit
bidirectional multiplexed address and data bus. During
external bus transfers, the AD Bus accommodates the transfer
of address and data information between the MA17501 and
memory, or l/O ports. During internal bus operations, the AD
Bus provides additional communication among the Execution,
Control, Interrupt and Memory Management/Block Protection
Units. AD00 is the most significant bit position and AD15 is the
least significant bit position of both the 16-bit data and 16-bit
address. A high on this bus corresponds to a logic one and a
low corresponds to a logic zero.
Address information is valid on the bus at the AS high to-
low transition. The RD/WN signal indicates the MA17501 AD
Bus drivers state during the data portion of the bus cycle (DSN
low) and the M/lON function defines the type of device the
transfer is with. The AD Bus drivers are placed in the high
impedance state during Read operations (DSN low), during
DMA cycles by PAUSEN low, and during the Hold state by
HLDAKN low.
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