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參數(shù)資料
| 型號： | M906-01I187.5000 |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 187.5 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| 封裝： | 9 X 9 MM, LEAD FREE, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 352K |
| 代理商： | M906-01I187.5000 |
M906-01 Datasheet Rev 3.2
3 of 8
Revised 15Jun2006
Integ r ated Circuit Systems, Inc. ● Communications Modules ● www.ics t.com ● tel (508) 852-5400
M906-01
VCSO BASED GBE CLOCK GENERATOR
Prod uct Data Sh eet
FUNCTIONAL DESCRIPTION
The M906-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M906-01 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The input reference can either be an external, discrete
crystal device or a stable external clock source such as
a packaged crystal oscillator:
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the XTAL_1 / REF_IN and XTAL_2 input
pins. External crystal load capacitors are also
required.
If an external LVCMOS/LVTTL clock source is used,
apply it to the XTAL_1 / REF_IN input pin.
In either case, the reference clock is supplied to the
phase detector of the PLL. The M906-01 includes a
reference divider that divides the input reference
frequency by a fixed value “R” and provides the result to
the phase detector.
The EX_CLK pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
on pg. 3.
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, a feedback divider (labeled
“M Divider”), and a reference divider (“R Divider”).
The feedback divider divides the VCSO output
frequency by a fixed value “M” to match the reference
frequency provided to the phase detector by the
reference divider.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the
reference divider output. This creates an output
frequency that is a multiple of the reference frequency
(which is output from the VCSO).
The relationship between the VCSO output frequency,
the M Divider, the R Divider and the input reference
frequency is defined as follows:
For the M906-01-156.2500 (see “Ordering Information” on pg. 8):
VCSO output frequency = 156.25MHz
Input reference frequency = 25MHz
M=25
R= 4
Therefore, for the M906-01-156.2500:
25
156.25MHz = 25MHz
4
The product of the input crystal frequency and
falls within the lock range of the VCSO.
External Clock Feed-through
The EXT_CLK pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. It can be used for system debugging and
performance evaluation.
1. Set pin EN_EXT_CLK to Logic 1.
2. Apply an external LVCMOS/LVTTL clock source
to the EXT_CLK input pin.
Due to the fact that EXT_CLK bypasses the PLL, any
frequency between DC and 200MHz can be used.
STOP Clock
The STOP pin puts the output clock into a static condition.
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
Fvcso
Fxtal M
R
-----
×
=
----------
×
M
R
-----
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M906-01I156.2500LF | 156.25 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01I125.0000 | 125 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01-190.0000 | 190 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01-187.5000 | 187.5 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01-156.2500LF | 156.25 MHz, OTHER CLOCK GENERATOR, CQCC36 |
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