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參數(shù)資料
| 型號(hào)： | M901-01-669.3266LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 669.3266 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 334K |
| 代理商： | M901-01-669.3266LF |
M901-01 Datasheet Rev 4.0
Revised 30Jul2004
Integr a t ed Cir cui t S ystems , Inc . ● N e tw or kin g & C o mm un icat ion s ● www. icst.com ● te l (5 08 ) 85 2-5 4 0 0
M901-01
VCSO BASED CLOCK GENERATOR
Product Data Sheet
GENERAL DESCRIPTION
The M901-01 is a PLL (Phase Locked Loop) based
clock generator that uses an internal
VCSO (Voltage Controlled SAW
Oscillator) to produce a very low
jitter output clock. The output clock
(e.g., frequencies of 622.08, 311.04,
155.52
, or 77.76MHz with the
M901-01-622.0800
) is provided from a
LVPECL clock output pair. Output frequency accuracy
is assured by phase-locking the VCSO to an external
input reference frequency (e.g., frequencies of 19.44,
38.80
, 77.76, or 155.52MHz with the M901-01-622.0800).
The input reference can either be an external crystal,
utilizing the internal crystal oscillator, or a stable
external clock source such as a packaged crystal
oscillator.
FEATURES
◆ Output clock frequency from 62MHz to 700MHz
(Consult factory for VCSO frequency availability)
◆ Low jitter 0.5ps rms, typ. (12kHz-20MHz @622.08MHz)
◆ Ideal for OC-48 (STM-16), Gigabit Ethernet clock ref
◆ Integrated SAW (surface acoustic wave) delay line
◆ XTAL or LVCMOS reference input
◆ LVPECL output
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
BLOCK DIAGRAM
Figure 2: Block Diagram
Note *: Other frequencies available. See “Ordering Information” on pg. 8.
Example Output Frequency Configurations *
Ref Clock
Freq
(MHz)
VCSO
Freq 1
(MHz)
Note1: Specify VCSO center frequency at time of order
Output
Freq
(MHz)
Application
19.44
622.08
OC-12/48
(STM-4/16)
155.52
25.00
625.00
156.25
10GbE
OP
nO
M Divider
M901-01
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
R
IN
R
IN
OP_IN
nOP_IN
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
FOUT
nFOUT
5
M5:2, M 0
P Divider
2
P1:0
OUT_EN
M1=0
XTAL_2
XTAL_1 / REF_IN
XTAL
OSC
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