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參數(shù)資料
| 型號： | M8813F3Y-90T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 56/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3Y-90T1 |
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M88 FAMILY
6/85
Page Register
The eight-bit Page Register expands the address
range of the microcontroller by up to 256 times.
The paged address can be used as part of the
address space to access external memory and
peripherals, or internal memory and I/O. The Page
Register can also be used to change the address
mapping of blocks of Flash memory into different
memory spaces for in-circuit reprogramming.
PLDs
The device contains two PLD blocks, each
optimized for a different function, as shown in
Table 4. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/
performance, and eases design entry.
The Decode PLD (DPLD) is used to decode
addresses and to generate chip selects for the
M88x3Fxx FLASH+PSD internal memory and
registers. The CPLD can implement user-defined
logic functions. The DPLD has combinatorial
outputs. The CPLD has 16 Output Macrocells and
3
combinatorial
outputs.
The
M88x3Fxx
FLASH+PSD also has 24 Input Macrocells that
can be configured as inputs to the PLDs. The
PLDs receive their inputs from the PLD Input Bus
and are differentiated by their output destinations,
number of Product Terms, and Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the microcontroller at run-time. There is a
slight penalty to PLD propagation time when
invoking the power management features.
I/O Ports
The M88x3Fxx FLASH+PSD has 27 I/O pins
distributed over the four ports (Port A, B, C, and
D). Each I/O pin can be individually configured for
different functions. Ports A, B, C and D can be
configured as standard MCU I/O ports, PLD I/O, or
latched address outputs for microcontrollers using
multiplexed address/data buses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus or multiplexed
address/data bus
for certain
types of
8-bit
microcontrollers.
Microcontroller Bus Interface
The M88x3Fxx FLASH+PSD easily interfaces with
most
8-bit microcontrollers that
have
either
multiplexed
or
non-multiplexed
address/data
buses. The device is configured to respond to the
microcontroller’s control signals, which are also
used as inputs to the PLDs. Where there is a
requirement to use a 16-bit data bus to interface to
a 16-bit microcontroller, two PSDs must be used.
The section entitled “Microcontroller Interface
Examples”, on page 35, contains microcontroller
interface examples.
Table 4. PLD I/O
Name
Abbreviation
Inputs
Outputs
Product
Terms
Decode
PLD
DPLD
73
17
42
Complex
PLD
CPLD
73
19
140
Table 5. JTAG SIgnals on Port C
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Table 6. Methods of Programming Different Functional Blocks of the M88 Family
Fun ctional Block
JTAG Programming
Device Programmer
In-System Parallel Programming
Main Flash memory
Yes
Optional EEPROM/Flash Boot
memory
Yes
PLD Array (DPLD and CPLD)
Yes
No
PSD Configuration
Yes
No
Optional OTP Row
No
Yes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M88141W-15K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-15K6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-15T1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-15T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-90K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
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