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參數(shù)資料
| 型號： | M8813F3W-15K1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 33/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3W-15K1 |
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39/85
M88 FAMILY
Figu re 27. General I/O Port Architecture
INTERNAL
DATA
BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
EXT CS
ALE
READ MUX
P
D
B
CPLD- INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
AI02885
have burst cycles. Address bits A[3:0] are not
multiplexed, while A[19:4] are multiplexed with
data bits D[15:0] in 16-bit mode. In 8-bit mode,
A[11:4] are multiplexed with data bits D[7:0].
The 80C51XA can be configured to operate in
eight-bit data mode. (shown in Figure 25).
The 80C51XA improves bus throughput and
performance by executing Burst cycles for code
fetches. In Burst Mode, address A19-4 are latched
internally by the M88x3Fxx FLASH+PSD, while
the 80C51XA changes the A3-0 lines to fetch up to
16 bytes of code. The PSD access time is then
measured from address A3-A0 valid to data in
valid. The PSD bus timing requirement in Burst
Mode is identical to the normal bus cycle, except
the address setup and hold time with respect to
ALE does not apply.
68HC11
Figure 26 shows an interface to a 68HC11 where
the M8813F1x is configured in 8-bit multiplexed
mode with E and R/W settings. The DPLD can
generate the READ and WR signals for external
devices.
I/O Ports
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft
Configuration or by the microcontroller writing to
on-chip registers in the CSIOP address space.
The topics discussed in this section are:
s
General Port Architecture
s
Port Operating Modes
s
Port Configuration Registers
s
Port Data Registers
s
Individual Port Functionality.
General Port Architecture
The general architecture of the I/O Port is shown
in Figure 27. Individual Port architectures are
shown in Figure 29 to Figure 32. In general, once
the purpose for a port pin has been defined, that
pin will no longer be available for other purposes.
Exceptions will be noted.
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| M8803F3Y-90K1T | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
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相關代理商/技術參數(shù) |
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| M88141W-15T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
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