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參數(shù)資料
| 型號： | M8813F2Y-90T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 1/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F2Y-90T1 |
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PRELIMINARY DATA
January 2000
M88 FAMILY
In-System Programmable (ISP)
Multiple-Memory and Logic FLASH+PSD Systems for MCUs
s
Single Supply Voltage:
–5 V
±10% for M88x3FxY
– 3 V (+20/–10%) for M88x3FxW
s
Fast Access Time:
–90 ns or 150 ns at 5 V
– 150 ns at 3 V
s
1 Mbit (128K x 8) Flash memory
– 8 uniform blocks of 16K x 8 each
s
A second non-volatile memory:
– 256 Kbit (32K x 8) EEPROM (for M8813F1x)
or Flash memory (for M88x3F2x)
– 4 uniform blocks
s
16 Kbit (2K x 8) SRAM for M8813Fxx (not
available on M8803Fxx)
s
Over 3,000 Gates of PLD
s
Reconfigurable I/O ports
s
JTAG Interface
s
Programmable power management
s
High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
Figu re 1. Logic Diagram
AI02856
16
AD0-AD15
PC0-PC7
VCC
FLASH+PSD
VSS
8
PD0-PD2
3
PB0-PB7
8
PA0-PA7
8
3
CNTL0-
CNTL2
RESET
Table 1. Signal Names
PA0-PA7
Port-A Data Lines
PB0-PB7
Port-B Data Lines
PC0-PC7
Port-C Data Lines
PC2 = Voltage Stand-by
PD0-PD2
Port-D Data Lines
AD0-AD15
Address/Data Lines
CNTL0-CNTL2
Control Lines
CNTL1 = CLOCK IN
RESET
Reset
VCC
Supply Voltage
VSS
Ground
PLCC52 (K)
PQFP52 (T)
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