- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180241 > M7A3P600-FPQG208 FPGA, 600000 GATES, 350 MHz, PQFP208 PDF資料下載
參數(shù)資料
| 型號(hào)： | M7A3P600-FPQG208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, 350 MHz, PQFP208 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 183/246頁(yè) |
| 文件大?。?/td> | 3010K |
| 代理商： | M7A3P600-FPQG208 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)當(dāng)前第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)
ProASIC3/E Flash Family FPGAs
v2.1
2-29
synchronous to RCLK to inhibit reading immediately
upon detection of an empty condition and to prevent
underflows. Since the read address is compared to a
resynchronized (and thus time-delayed) version of the
write address, the EMPTY flag will remain asserted until
two RCLK active edges after a write operation removes
the empty condition.
For more information on these signals, refer to the "FIFO
AFULL, AEMPTY
These are programmable flags and will be asserted on
the
threshold
specified
by
AFVAL
and
AEVAL,
respectively.
When the number of words stored in the FIFO reaches
the amount specified by AEVAL while reading, the
AEMPTY output will go HIGH. Likewise, when the
number of words stored in the FIFO reaches the amount
specified by AFVAL while writing, the AFULL output will
go HIGH.
AFVAL, AEVAL
The AEVAL and AFVAL pins are used to specify the
almost-empty and almost-full threshold values. They are
12-bit signals. For more information on these signals,
refer to the "FIFO Flag Usage Considerations" section on
ESTOP and FSTOP Usage
The ESTOP pin is used to stop the read counter from
counting any further once the FIFO is empty (i.e., the
EMPTY flag goes HIGH). Likewise, the FSTOP pin is used
to stop the write counter from counting any further once
the FIFO is full (i.e., the FULL flag goes HIGH).
The FIFO counters in the ProASIC3 device start the count
at zero, reach the maximum depth for the configuration
(e.g., 511 for a 512×9 configuration), and then restart at
zero. An example application for ESTOP, where the read
counter keeps counting, would be writing to the FIFO
once and reading the same content over and over
without doing another write.
FIFO Flag Usage Considerations
The AEVAL and AFVAL pins are used to specify the 12-bit
AEMPTY and AFULL threshold values. The FIFO contains
separate 12-bit write address (WADDR) and read address
(RADDR) counters. WADDR is incremented every time a
write operation is performed, and RADDR is incremented
every time a read operation is performed. Whenever the
difference between WADDR and RADDR is greater than
or equal to AFVAL, the AFULL output is asserted.
Likewise, whenever the difference between WADDR and
RADDR is less than or equal to AEVAL, the AEMPTY
output is asserted. To handle different read and write
aspect ratios, AFVAL and AEVAL are expressed in terms
of total data bits instead of total data words. When users
specify AFVAL and AEVAL in terms of read or write
words, the SmartGen tool translates them into bit
addresses and configures these signals automatically.
SmartGen configures the AFULL flag to assert when the
write address exceeds the read address by at least a
predefined value. In a 2k×8 FIFO, for example, a value of
1,500 for AFVAL means that the AFULL flag will be
asserted after a write when the difference between the
write address and the read address reaches 1,500 (there
have been at least 1,500 more writes than reads). It will
stay asserted until the difference between the write and
read addresses drops below 1,500.
The AEMPTY flag is asserted when the difference
between the write address and the read address is less
than a predefined value. In the example above, a value
of 200 for AEVAL means that the AEMPTY flag will be
asserted when a read causes the difference between the
write address and the read address to drop to 200. It will
stay asserted until that difference rises above 200. Note
that the FIFO can be configured with different read and
write widths; in this case the AFVAL setting is based on
the number of write data entries, and the AEVAL setting
is based on the number of read data entries. For aspect
ratios of 512×9 and 256×18, only 4,096 bits can be
addressed by the 12 bits of AFVAL and AEVAL. The
number of words must be multiplied by 8 and 16 instead
of 9 and 18. The SmartGen tool automatically uses the
proper values. To avoid halfwords being written or read,
which could happen if different read and write aspect
ratios are specified, the FIFO will assert FULL or EMPTY as
soon as at least a minimum of one word cannot be
written or read. For example, if a two-bit word is written
and a four-bit word is being read, the FIFO will remain in
the empty state when the first word is written. This
occurs even if the FIFO is not completely empty, because
in this case a complete word cannot be read. The same is
applicable in the full state. If a four-bit word is written
and a two-bit word is read, the FIFO is full and one word
is read. The FULL flag will remain asserted because a
complete word cannot be written at this point.
Refer to the ProASIC3/E SRAM/FIFO Blocks application
note for more information.
Advanced I/Os
Introduction
ProASIC3
devices
feature
a
flexible
I/O
structure,
supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V,
and 3.3 V) through a bank-selectable voltage. Table 2-11,
Table 2-12, and Table 2-19 on page 2-47 show the
voltages and the compatible I/O standards. I/Os provide
programmable
slew
rates
(except
A3P030),
drive
strengths, and weak pull-up and pull-down circuits. 3.3 V
PCI and 3.3 V PCI-X are 5 V–tolerant. See the "5 V Input
for
possible
implementations of 5 V tolerance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3P600-PQ208I | FPGA, 600000 GATES, 350 MHz, PQFP208 |
| M7A3P600-PQ208 | FPGA, 600000 GATES, 350 MHz, PQFP208 |
| M7A3P600-PQG208I | FPGA, 600000 GATES, 350 MHz, PQFP208 |
| M7A3P600-PQG208 | FPGA, 600000 GATES, 350 MHz, PQFP208 |
| M7A3P600-1FG144I | FPGA, 600000 GATES, 350 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。