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鍨嬭櫉锛� M7A3P1000-FG256
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鎻忚堪锛� IC FPGA 1KB FLASH 1M 256-FBGA
妯欐簴鍖呰锛� 90
绯诲垪锛� ProASIC3
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 177
闁€鏁�(sh霉)锛� 1000000
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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ProASIC3 Flash Family FPGAs
Revision 13
2-45
Table 2-55 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
Equiv.
Software
Default
Drive
Strength
Option1
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
100 A
2 mA
Std.
0.60
14.64
0.04 1.52
0.43
14.64
12.97
3.21 3.15
ns
鈥�1
0.51
12.45
0.04 1.29
0.36
12.45
11.04
2.73 2.68
ns
鈥�2
0.45
10.93
0.03 1.13
0.32
10.93
9.69
2.39 2.35
ns
100 A
4 mA
Std.
0.60
14.64
0.04 1.52
0.43
14.64
12.97
3.21 3.15
ns
鈥�1
0.51
12.45
0.04 1.29
0.36
12.45
11.04
2.73 2.68
ns
鈥�2
0.45
10.93
0.03 1.13
0.32
10.93
9.69
2.39 2.35
ns
100 A
6 mA
Std.
0.60
10.16
0.04 1.52
0.43
10.16
9.08
3.71 3.98
ns
鈥�1
0.51
8.64
0.04 1.29
0.36
8.64
7.73
3.15 3.39
ns
鈥�2
0.45
7.58
0.03 1.13
0.32
7.58
6.78
2.77 2.97
ns
100 A
8 mA
Std.
0.60
10.16
0.04 1.52
0.43
10.16
9.08
3.71 3.98
ns
鈥�1
0.51
8.64
0.04 1.29
0.36
8.64
7.73
3.15 3.39
ns
鈥�2
0.45
7.58
0.03 1.13
0.32
7.58
6.78
2.77 2.97
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞PDF璩囨枡
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