2-14 Revision 13 User I/O Characteristics Timing Model Figure 2-2 Timing Model " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� M7A3P1000-2PQG208
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 142/220闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 1M 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 154
闁€鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
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ProASIC3 DC and Switching Characteristics
2-14
Revision 13
User I/O Characteristics
Timing Model
Figure 2-2 Timing Model
Operating Conditions: 鈥�2 Speed, Commercial Temperature Range (TJ = 70掳C), Worst Case
VCC = 1.425 V
DQ
Y
DQ
Y
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL (Applicable to
Advanced I/O Banks Only)L
LVPECL
(Applicable
to Advanced
I/O Banks only)
LVDS,
BLVDS,
M-LVDS
(Applicable for
Advanced I/O
Banks only)
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTLOutput drive strength = 8 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5 VOutput drive strength = 4 mA
High slew rate
LVTTLOutput drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL
Clock
Input LVTTL
Clock
Input LVTTL
Clock
tPD = 0.56 ns
tPD = 0.49 ns
tDP = 1.34 ns
tPD = 0.87 ns
tDP = 2.64 ns (Advanced I/O Banks)
tPD = 0.47 ns
tDP = 3.66 ns (Advanced I/O Banks)
tPD = 0.47 ns
tDP = 3.97 ns (Advanced I/O Banks)
tPD = 0.47 ns
tPY = 0.76 ns
(Advanced I/O Banks)
tCLKQ = 0.55 ns
tOCLKQ = 0.59 ns
tSUD = 0.43 ns
tOSUD = 0.31 ns
tDP = 2.64 ns
(Advanced I/O Banks)
tPY = 0.76 ns (Advanced I/O Banks)
tPY = 1.20 ns
tCLKQ = 0.55 ns
tSUD = 0.43 ns
tPY = 0.76 ns
(Advanced I/O Banks)
tICLKQ = 0.24 ns
tISUD = 0.26 ns
tPY = 1.05 ns
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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