2-58 Revision 13 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� M7A3P1000-1PQG208
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 191/220闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 1M 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 154
闁€鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
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ProASIC3 DC and Switching Characteristics
2-58
Revision 13
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-75 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.66
15.01
0.04
1.20
0.43
13.15
15.01
1.99
ns
鈥�1
0.56
12.77
0.04
1.02
0.36
11.19
12.77
1.70
ns
鈥�2
0.49
11.21
0.03
0.90
0.32
9.82
11.21
1.49
ns
4 mA
Std.
0.66
10.10
0.04
1.20
0.43
9.55
10.10
2.41
2.37
ns
鈥�1
0.56
8.59
0.04
1.02
0.36
8.13
8.59
2.05
2.02
ns
鈥�2
0.49
7.54
0.03
0.90
0.32
7.13
7.54
1.80
1.77
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-76 Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.,
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3 A4 A4
2 mA
鈥�0.3
0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI
2
16
13
10 10
4 mA
鈥�0.3
0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI
4
33
25
10 10
6 mA
鈥�0.3
0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI 6
6
39
32
10 10
8 mA
鈥�0.3
0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI 8
8
55
66
10 10
12 mA
鈥�0.3
0.35 * VCCI
0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI 12 12
55
66
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at high temperature (100掳C junction temperature) and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
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