
DDR for Actel’s Low-Power Flash Devices
v1.1
9 - 9
DDR Tristate Output Register
Verilog
module DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp(DataR, DataF, CLR, CLK, Trien,
PAD);
input
DataR, DataF, CLR, CLK, Trien;
output
PAD;
wire TrienAux, Q;
INV Inv_Tri(.A(Trien),.Y(TrienAux));
DDR_OUT DDR_OUT_0_inst(.DR(DataR),.DF(DataF),.CLK(CLK),.CLR(CLR),.Q(Q));
TRIBUFF_F_8U TRIBUFF_F_8U_0_inst(.D(Q),.E(TrienAux),.PAD(PAD));
endmodule
VHDL
library ieee;
use ieee.std_logic_1164.all;
library proasic3; use proasic3.all;
entity DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp is
port(DataR, DataF, CLR, CLK, Trien : in std_logic;
PAD : out std_logic) ;
end DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp;
architecture DEF_ARCH of DDR_TriStateBuf_LVTTL_8mA_HighSlew_LowEnb_PullUp is
component INV
port(A : in std_logic := 'U'; Y : out std_logic) ;
end component;
component DDR_OUT
port(DR, DF, CLK, CLR : in std_logic := 'U'; Q : out std_logic) ;
end component;
component TRIBUFF_F_8U
port(D, E : in std_logic := 'U'; PAD : out std_logic) ;
end component;
signal TrienAux, Q : std_logic ;
begin
Inv_Tri : INV
Figure 9-7
DDR Tristate Output Register, LOW Enable, 8 mA, Pull-Up (LVTTL)
Q
PAD
DR
Q
CLR
DF
DataR
DataF
CLR
CLK
TRIBUFF_F_8U
DDR_OUT
Trien
AY
T
rienAux
INV