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參數(shù)資料
| 型號(hào)： | M74HCT7259M1R |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 鎖存器 |
| 英文描述： | HCT SERIES, LOW LEVEL TRIGGERED D LATCH, INVERTED OUTPUT, PDSO16 |
| 封裝： | SO-16 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 317K |
| 代理商： | M74HCT7259M1R |
1/13
September 2001
s
LOW POWER DISSIPATION:
ICC =4A(MAX.) at TA=25°C
s
COMPATIBLE WITH TTL OUTPUTS :
VIH = 2V (MIN.) VIL = 0.8V (MAX)
s
HIGH CURRENT OPEN DRAIN OUTPUT UP
TO 80 mA
DESCRIPTION
The M74HCT7259 is an high speed CMOS 8 BIT
ADDRESSABLE LATCH/DECODER fabricated
with silicon gate C2MOS technology.
This device has single data input (D) 8 LATCH
inverted OUTPUTS (Q0 - Q7), 3 address inputs
(A, B and C), common enable input (ENABLE)
and a common CLEAR input. To operate this
device as an addressable latch, data is held on the
D input, and the address of the latch into which the
data is to be entered is held on the A, B and C
inputs.
When ENABLE is taken low the data flows
through to the address output. The data is stored
on the positive going edge of the ENABLE pulse.
All unaddressed latches will remain unaffected.
With ENABLE in the high state the device is
deselected and all latches remain in their previous
state, unaffected by changes on the data or
address inputs. To eliminate the possibility of
entering erroneous data into the latches, the
ENABLE should be held high (inactive) while the
address lines are changing. If ENABLE is held
high and CLEAR is taken low all eight latches are
cleared to the HIGH (OFF) state. If ENABLE is low
all latches except the addressed latch will be
cleared. The address latch will instead be the
complement
of
the
D
input,
effectively
implementing a 3 to 8 line decoder. Internal clamp
diodes protect the open drain outputs against over
voltages due to inductive loads.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT7259
8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER
OPEN DRAIN, INVERTING OUTPUT
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACK.
TUBE
T & R
DIP
M74HCT7259B1R
SOP
M74HCT7259M1R M74HCT7259RM13TR
TSSOP
M74HCT7259TTR
TSSOP
DIP
SOP
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PDF描述 |
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| M74HCT7259RM13TR | HCT SERIES, LOW LEVEL TRIGGERED D LATCH, INVERTED OUTPUT, PDSO16 |
| M74HCT75C1R | HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC20 |
| M74HCT75M1R | HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16 |
| M74LS03P | LS SERIES, QUAD 2-INPUT NAND GATE, PDIP14 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M74HCT7259RM13TR | 制造商:STMicroelectronics 功能描述:LATCH/DECODER/DRVR SGL 3-TO-8 16SOIC - Tape and Reel |
| M74HCT74B1 | 制造商:STMicroelectronics 功能描述:Flip Flop, Dual, D Type, 14 Pin, Plastic, DIP |
| M74HCT74B1R | 功能描述:觸發(fā)器 Dual "D" Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| M74HCT74M1R | 功能描述:觸發(fā)器 Dual "D" Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| M74HCT74RM13TR | 功能描述:觸發(fā)器 Dual "D" Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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