參數(shù)資料
型號(hào): M74HCT137M1R
廠商: STMICROELECTRONICS
元件分類: 編、解碼器及復(fù)用、解復(fù)用
英文描述: HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16
封裝: SOP-16
文件頁(yè)數(shù): 1/11頁(yè)
文件大?。?/td> 314K
代理商: M74HCT137M1R
1/11
September 2001
s
HIGH SPEED:
tPD =17ns (TYP.) at VCC = 4.5V
s
LOW POWER DISSIPATION:
ICC = 4A(MAX.) at TA=25°C
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 137
DESCRIPTION
The M74HCT137 is an high speed CMOS 3 TO 8
LINE DECODER/LATCH (INVERTING) fabricated
with silicon gate C2MOS technology.
This device is a 3 to 8 line decoder with latches on
the three address inputs. When GL goes from low
to high, the addresses present at the select inputs
(A, B, and C) is stored in the latches. As long as
GL remains high no address changes will be
recognized. Output enable pins G1 and G2,
control the state of the outputs independently of
the select or latch-enable inputs. All the outputs
are high unless G1 is high and G2 is low. The
74HCT137 is ideally suited for the implementation
of
glitch-free
decoders
in
stored-address
application in bus oriented systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT137
3 TO 8 LINE DECODER/LATCH (INVERTING)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HCT137B1R
SOP
M74HCT137M1R
M74HCT137RM13TR
TSSOP
M74HCT137TTR
TSSOP
DIP
SOP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M74HCT138B1 制造商:STMicroelectronics 功能描述:
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