參數(shù)資料
型號(hào)： M74HC40102B1R
廠商： STMICROELECTRONICS
元件分類： 計(jì)數(shù)器
英文描述： HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT DOWN DECADE COUNTER, PDIP16
封裝： PLASTIC, DIP-16
文件頁(yè)數(shù)： 9/16頁(yè)
文件大?。?/td> 659K
代理商： M74HC40102B1R
M74HC40102
2/16
asynchronously cleared to its maximum count
(9910) regardless of the state of any other input.
The precedence relationship between control
input is indicated in the truth table. If all control
inputs are high at the time of zero count, the
counters will jump to the maximum count giving a
INPUT AND OUTPUT EQUIVALENT CIRCUIT
counting sequence of 100 clock pulses long. The
HC40102 may be cascaded using the CI/CE input
and the CO/ZD output, in either a synchronous or
ripple
mode.
All
inputs
are
equipped
with
protection circuits against static discharge and
transient excess voltage.
PIN DESCRIPTION
TRUTH TABLE
X : Don’t Care
Maximum Count is "99"
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK
Clock Input (LOW to
HIGH edge triggered)
2
CLEAR
Asynchronous Master
Reset Input (Active Low)
3
CI/CE
Terminal Enable Input
4, 5, 6, 7, 10,
11, 12, 13
J0 to J9
Jam Inputs
9APE
Asynchronous Preset
Enable Inputs(Active Low)
14
CO/ZD
Terminal Count Output
(Active Low)
15
SPE
Synchronous Preset
Enable Input (Active Low)
8
GND
Ground (0V)
16
Vcc
Positive Supply Voltage
CONTROL INPUTS
MODE
FUNCTIONAL DESCRIPTION
CLEAR
APE
SPE
CI/CE
H
COUNT INHIBIT
EVEN IF CLOCK IS GIVEN, NO COUNT IS MADE
H
L
REGULAR COUNT
DOWN COUNT AT RISING EDGE OF CLOCK
HH
L
X
SYNCHRONOUS
PRESET
DATA OF PI TERMINAL IS PRESET AT RISING
EDGE OF CLOCK
HL
XX
ASYNCHRONOUS
PRESET
DATA OF PI TERMINAL IS ASYNCHRONOUSLY
PRESET TO CLOCK
L
X
CLEAR
COUNTER IS SET TO MAXIMUM COUNT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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