參數(shù)資料
型號(hào)： M68Z512NC
廠商： 意法半導(dǎo)體
英文描述： 4 Mbit 512Kb x8 Low Power SRAM with Output Enable
中文描述： 4兆位512KB的x8與輸出低功耗SRAM啟用
文件頁數(shù)： 1/12頁
文件大小： 92K
代理商： M68Z512NC
1/12
March 2000
M68Z512
4 Mbit (512Kb x8) Low Power SRAM with Output Enable
I
ULTRA LOW DATA RETENTION CURRENT
– 100nA (typical)
– 10μA (max)
I
OPERATION VOLTAGE: 5V ±10%
I
512 Kbit x8 SRAM with OUTPUT ENABLE
I
EQUAL CYCLE and ACCESS TIMES: 70ns
I
LOW V
CC
DATA RETENTION: 2V
I
TRI-STATE COMMON I/O
I
CMOS for OPTIMUM SPEED/POWER
I
AUTOMATIC POWER-DOWN WHEN
DESELECTED
I
INTENDED FOR USE WITH ST
ZEROPOWER
AND TIMEKEEPER
CONTROLLERS
DESCRIPTION
The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS
SRAM, organized as 524,288 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
5V ±10% supply, and all inputs and outputs are
TTL compatible.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68Z512 is available in a 32 lead TSOP II
(10 x 20mm) package.
Figure 1. Logic Diagram
AI03030
19
A0-A18
W
DQ0-DQ7
VCC
M68Z512
G
VSS
8
E
32
1
TSOP II 32 (NC)
10 x 20mm
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Output
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
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