參數(shù)資料
型號： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁數(shù)： 12/52頁
文件大小： 358K
代理商： M68HC16
MOTOROLA
12
AN1283/D
3.3 Data Types
The CPU16 uses the following types of data:
Bits
4-bit signed integers
8-bit (byte) signed and unsigned integers
8-bit, 2-digit binary coded decimal numbers
16-bit (word) signed and unsigned integers
32-bit (long word) signed and unsigned integers
16-bit signed fractions
32-bit signed fractions
36-bit signed fixed-point numbers
20-bit effective address consisting of 16-bit byte address and 4-bit extension
There are 8 bits in a byte, 16 bits in a word. Bit set and clear instructions use both byte and word operands.
Bit test instructions use byte operands.
Negative integers are represented in two's-complement form. Four-bit signed integers, packed two to a
byte, are used only as X and Y offsets in MAC and RMAC operations. Thirty-two-bit integers are used only
by extended multiply and divide instructions, and by the associated LDED and STED instructions.
Binary coded decimal numbers are packed, two digits per byte. BCD operations use byte operands.
16-bit fractions are used in both fractional multiplication and division, and as multiplicand and multiplier op-
erands in the MAC unit. Bit 15 is the sign bit. There is an implied radix point between bits 15 and 14. There
are 15 bits of magnitude — the range of values is –1 ($8000) to 1 – 2
-15
($7FFF).
Signed 32-bit fractions are used only by fractional multiplication and division instructions. Bit 31 is the sign
bit. An implied radix point lies between bits 31 and 30. There are 31 bits of magnitude — the range of values
is –1 ($80000000) to 1 – 2
($7FFFFFFF).
-31
Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit. Bits [34:31] are sign
extension bits. There is an implied radix point between bits 31 and 30. There are 31 bits of magnitude, but
use of the extension bits allows representation of numbers in the range –16 ($800000000) to 15.999969482
($7FFFFFFFF).
20-bit addresses are formed by combining a 16-bit byte address with a 4-bit address extension.
3.4 Memory Organization
A word is composed of two consecutive bytes. A word address is normally an even byte address. Byte 0 of
a word has a lower 16-bit address than Byte 1. Long words and 32-bit signed fractions consist of two con-
secutive words, and are normally accessed at the address of Byte 0 in Word 0.
Instruction fetches always access word addresses. Word operands are normally accessed at even byte ad-
dresses, but may be accessed at odd byte addresses, with a substantial performance penalty.
To be compatible with the M68HC11 CPU, misaligned word transfers and misaligned stack accesses are
allowed. Transferring a misaligned word requires two successive byte transfer operations.
3.5 Addressing Modes
The CPU16 uses 9 basic types of addressing. There are one or more addressing modes within each type.
Table 5
shows the addressing modes.
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