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參數(shù)資料
| 型號： | M66271FP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 320 X 240 DOTS DOT MAT LCD DSPL CTLR, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大小： | 309K |
| 代理商： | M66271FP |
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M66271FP
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 7 of 27
(2) Accessing to VRAM
Item
Symbol
Min
Typ
Max
Unit
MCS pulse width
WR pulse width
tW (MCS)
tW (WR)
70
—
ns
Data set up time before falling edge of MCS
Data set up time before falling edge of WR
tsu (D-MCS)
tsu (D-WR)
0
—
ns
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
th (MCS-D)
th (WR-D)
15
—
ns
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
tsu (A-MCS)
tsu (A-WR)
tsu (A-RD)
15
—
ns
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
th (MCS-A)
th (WR-A)
th (RD-A)
15
—
ns
(3) Clock and Accessing to LCD Display
Item
Symbol
Min
Typ
Max
Unit
MPUCLK cycle time
tC (CLK)
50
—
ns
MPUCLK "H" pulse width
tWH (CLK)
MPUCLK "L" pulse width
tWL (CLK)
—
tC (CLK)
2
—
ns
OSC cycle time
tC (OSC)
50*
—
ns
OSC "H'' pulse width
tWH (OSC)
OSC "L" pulse width
tWL (OSC)
—
tC (OSC)
2
—
ns
CP cycle time
tC (CP)
—
tC (OSC)
(1/n)
—
ns
CP "H" pulse width
tWH (CP)
CP "L" pulse width
tWL (CP)
—
tC (OSC)
2
(1/n)
—
ns
FLM pulse width
tW (FLM)
—
2
t
C (OSC) LPW
(1/n)
—
ns
Note:
Clock frequency of OSC1 input is less than fmax = 20 MHz.
Limit of OSC clock for the internal operation is fmax = 10 MHz.
When OSC1 is more than 10 MHz from external input, set OSC clock up to 10 MHz by using division of OSCC
register.
Division is set with rising edge of OSC1 input.
1/n = Division of OSC1
LPW = Setting value of LPW register
Test Circuit
Item
SW1
SW2
tdis (LZ)
Closed
Open
tdis (HZ)
Open
Closed
ta (ZL)
Closed
Open
ta (ZH)
Open
Closed
P.G
DUT
Input
VDD
VSS
50
Outputs
except for
D <15:0>
SW1
SW2
RL = 1 k
CL
(1) Input pulse level: 0 to 3 V
Input pulse rise/fall time: tr, tf = 3 ns
Input decision voltage: 1.5 V
Output decision voltage: VDD/2
(However, tdis (LZ) is 10% of output amplitude and tdis
(HZ) is 90% of that for decision.)
(2) Load capacity CL include float capacity of
connection and input capacity of probe.
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