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參數(shù)資料
| 型號： | M66004SP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 36 X 16 DOTS FLUORESCENT DSPL CTRL, PDIP64 |
| 封裝： | PLASTIC, DIP-64 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 3009K |
| 代理商： | M66004SP |
M66238FP
REJ03F0268-0200 Rev.2.00 Mar 18, 2008
Page 9 of 14
3. Dummy trigger generating command
The internal status of sync clock generator becomes unstable and a stable sync clock output (CKO) is not obtained
after the power is turned on, after a reset is cleared or after an internal VCO oscillator frequency is set. To obtain a
stable sync clock output, enter a trigger signal from the TR input after VCO oscillator becomes stable, or enter a
dummy trigger generating command from the MCU. The PLL synthesizer oscillator frequency after the cancellation
of a reset depends on a default (See the register configuration).
Set the command for address (A1, A0) = (1, 1).
Data Bit
Description
Default
0
D0
1
The command must be stored two times continuously when a dummy trigger is
generated. For the first time, set the dummy trigger generating command with D0 = 1.
For the second time, set the dummy trigger generating command with D0 = 0.
The second setting becomes a sync edge and a clock begins to be output from CKO.
After the first setting, CKO is in the halt state.
0
D1
1
0
↓
0
D29
1
In normal use: "0"
0
Operating Timing
1. Sync Clock Spike Non-removal Mode upon Occurrence of Trigger
1.1 Setting of Trigger Edge when D1 = 0
One-shot pulse start timing:
1st leading edge of CKO after TR fall
One-shot pulse polarity:
Negative pulse
One-shot pulse width:
16 cycles of CKO
CKO output dividing ratio:
1/2 division
An example set for the condition of address (A1, A0) = (1, 0), data (D6, D5, D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0, 0, 0)
is shown below. CKO is a clock output synchronized by TR and PULSE is a one-shot pulse synchronized with the rise
of CKO.
Internal VCO
oscillator clock
tp = 1 / fvco
tp = 1 / fout
tlp
tw (TR)
tsp (CKO)
tss (CKO)
tw (PULSE)
tss (PULSE)
SPIKE
t
TR
CKO
PULSE
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