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參數(shù)資料
| 型號： | M5M5W816WG-85H |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| 中文描述： | 8388608位（524288字由16位）的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 87K |
| 代理商： | M5M5W816WG-85H |
MITSUBISHI ELECTRIC
M5M5W816WG -85L, 10L, 85H, 10H
-85LI, 10LI, 85HI, 10HI
1999.1.15
Ver. 0.1
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Some parametric limits are subject to change
AC ELECTRICAL CHARACTERISTICS
(Vcc=1.8 ~ 2.7V, unless otherwise noted)
(1) TEST CONDITIONS
Input rise time and fall time
Reference level
Output loads
1.8~2.7V
V
IH
=0.7 x Vcc, V
IL
=0.2V
5ns
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Supply voltage
Input pulse
1TTL
CL
DQ
Fig.1 Output load
Including scope and
jig capacitance
t
CR
t
a
(A)
ns
ns
ns
ns
t
a
(S1)
t
a
(S2)
t
a
(OE)
t
dis
(S1)
t
dis
(S2)
t
dis
(OE)
t
en
(S1)
t
en
(S2)
t
en
(OE)
t
V
(A)
10
10
45
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
a
(BC1)
t
a
(BC2)
t
dis
(BC1)
t
dis
(BC2)
t
dis
(BC1)
t
dis
(BC2)
ns
ns
ns
ns
85
85
85
85
85
30
30
30
10
10
5
10
100
10
10
50
35
35
100
100
100
100
100
35
35
35
10
10
5
10
85
85L, 85H,
85LI, 85HI
Min
4
t
su
(A-WH)
t
su
(BC1)
t
su
(BC2)
t
CW
t
w
(W)
t
su
(A)
t
su
(S1)
t
su
(S2)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
30
30
100
75
0
85
85
85
85
85
5
5
50
0
0
85
60
0
70
70
70
70
70
5
5
45
0
0
Symbol
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S1 high
Limits
Output disable time after S2 low
Output disable time after BC1 high
Output disable time after BC2 high
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after BC1 low
Output enable time after BC2 low
Output enable time after OE low
Data valid time after address
Max
Max
Min
Units
(2) READ CYCLE
(3) WRITE CYCLE
Max
Min
Max
Min
Limits
Units
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Byte control 1 setup time
Byte control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
Symbol
Parameter
V
OH
=V
OL
=0.9V
10L, 10H,
10LI, 10HI
85L, 85H,
85LI, 85HI
10L, 10H,
10LI, 10HI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M5W816WG-85L | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5W816WG-85LI | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5W816WG-10H | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5W816WG-10HI | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5W816WG-10L | 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM |
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