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| 型號： | M5M4V4405CTP-7S |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| 中文描述： | 江戶（超頁模式）4194304位（1048576 - Word的4位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 293K |
| 代理商： | M5M4V4405CTP-7S |
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EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
M5M4V4405CJ,TP-6,-7,-6S,-7S
MITSUBISHI LSIs
read/write cycles
refresh cycles
1024cycles
last
refresh Cycles
first
refresh cycles
refresh cycles
1024 cycles
refresh cycles
1024 cycles
Read / Write
Self Refresh
Read / Write
2. Burst refresh during Read/Write operation
(A) Timing diagram
Table 3
Read / Write Cycle
CBR burst
refresh
RAS only
burst refresh
Read / Write
Self Refresh
Definition of CBR burst refresh
The CBR burst refresh performs more than 1024
continuous CBR cycles within 16.4 ms.
(B) Definition of burst refresh
All combination of nine row address signals (A
0
~A
9
)
are selected during 1024 continuous RAS only refresh
cycles within 16.4 ms.
Definition of RAS only burst refresh
t
NSB
+t
SNB
≤
16.4ms
Self Refresh
Read / Write
t
NSB
≤
16.4ms
t
SNB
≤
16.4ms
2.1 CBR burst refresh
Switching from read/write operation to self refresh operation.
The time interval ns from the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within 16.4 ms.
Switching from self refresh operation to read/write operation.
The time interval snob from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the last CBR refresh cycle during read/write operation period
should be set within 16.4 ms.
16.4ms
RAS
t
NSB
t
RASS
≥
100μs
t
SNB
RAS
2.2 RAS only burst refresh
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the first
RAS only refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within t
NSB
(Shown in table 3).
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end of
self refresh operation to the falling edge of RAS signal in the last
RAS only refresh cycle during read/write operation period should
be set within t
SNB
(shown in table 3).
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