參數(shù)資料
型號(hào): M5M44265CTP-5S
廠商: Mitsubishi Electric Corporation
英文描述: EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
中文描述: 江戶(超頁模式)4194304位(262144字由16位)動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁數(shù): 1/31頁
文件大?。?/td> 319K
代理商: M5M44265CTP-5S
EDEDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44265CJ,TP-5,-6,-7,
MITSUBISHI LSIs
1
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with
Hyper Page mode fuction, fabricated with the high performance
CMOS process, and is ideal for the buffer memory systems of
personal computer graphics and HDD where high speed, low
power dissipation, and low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.
This device has 2CAS and 1W terminals with a refresh cycle of
512 cycles every 8.2ms.
FEATURES
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS Input level 5.5mW (Max)
CMOS Input level 550μW (Max)*
Operating power dissipation
M5M44265Cxx-5,-5S 688mW (Max)
M5M44265Cxx-6,-6S 605mW (Max)
M5M44265Cxx-7,-7S 523mW (Max)
Self refresh capability*
Self refresh current 150μA (Max)
Extended refresh capability
Extended refresh current 150μA (Max)
Hyper-page mode (512-column random access), Read-modify-
write, RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A
0
~A
8
)
512 refresh cycles every 128ms (A
0
~A
8
)*
Byte or word control for Read/Write operation (2CAS, 1W type)
*
: Applicable to self refresh version (M5M44265CJ,TP-5S,-6S,-7S
: option) only
XX=J,TP
Type name
RAS
(time
50
CAS
(time
13
(time
25
access
time
(min.ns)
90
Cycle
Power
(typ.mW)
625
tion
M5M44265CXX-7,-7S
M5M44265CXX-6,-6S
60
70
15
20
30
35
110
130
550
475
15
20
aOE
(time
13
M5M44265CXX-5,-5S
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame Buffer
memory for CRT
PIN CONFIGURATION (TOP VIEW)
1
9
2
3
4
5
11
10
12
13
40
39
38
37
36
30
32
31
29
28
DQ
1
A
0
A
1
A
2
A
3
(5V)V
CC
V
SS
(0V)
NC
A
8
A
7
A
6
A
5
A
4
W
RAS
UCAS
OE
Outline 40P0K (400mil SOJ)
6
7
8
35
34
33
16
18
17
19
20
14
15
25
23
24
22
21
27
26
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
(5V)V
CC
(5V)V
CC
NC
NC
LCAS
NC
DQ
12
DQ
11
DQ
10
DQ
9
V
SS
(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
1
9
2
3
4
5
13
10
14
15
44
43
42
41
40
32
36
35
31
30
DQ
1
A
0
A
1
A
2
A
3
(5V)V
CC
V
SS
(0V)
NC
A
8
A
7
A
6
A
5
A
4
W
RAS
UCAS
OE
Outline 44P3W-R (400mil TSOP Nomal Bend)
6
7
8
39
38
37
18
20
19
21
22
16
17
27
25
26
24
23
29
28
DQ
2
DQ
3
DQ4
DQ
5
DQ
6
DQ
7
DQ
8
(5V)V
CC
(5V)V
CC
NC
NC
LCAS
NC
DQ
12
DQ
11
DQ
10
DQ
9
V
SS
(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
NC: NO CONNECTION
-5S,-6S,-7S
PIN DESCRIPTION
Pin name
A
0
~A
8
DQ
1
~DQ
16
RAS
UCAS
W
OE
V
CC
V
SS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Upper byte control
column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
LCAS
相關(guān)PDF資料
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