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參數(shù)資料
| 型號： | M5M44265CJ-7S |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| 中文描述： | 江戶（超頁模式）4194304位（262144字由16位）動態(tài)隨機(jī)存儲器 |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 319K |
| 代理商： | M5M44265CJ-7S |
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EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
5
Read and Refresh Cycles
Note 22: Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
Limits
Min
90
50
8
40
13
Max
Parameter
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Symbol
t
RC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
t
RCH
t
RRH
t
RAL
t
CAL
Unit
Min
110
60
10
48
15
Max
Min
130
70
13
55
20
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
(Note 22)
(Note 22)
t
OCH
t
ORH
CAS hold time after OE low
RAS hold time after OE low
ns
ns
10000
10000
10000
10000
10000
10000
0
0
0
25
13
13
13
0
0
0
30
18
15
15
0
0
0
35
23
20
20
M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S
Limits
Min
Max
8.2
128
Parameter
Refresh cycle time
Refresh cycle time
*
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Symbol
t
REF
t
REF
Unit
Min
Max
8.2
128
Min
Max
8.2
128
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
DZO
t
RDD
(Note 20)
(Note 20)
(Note 21)
(Note 16)
(Note 17)
(Note 18)
ns
t
T
Transition time
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Hyper-Page Mode Cycles)
(Ta=0~70C, V
CC
=5V±10%, V
SS
=0V, unless otherwise noted, see notes 14,15)
(Note 19)
(Note 20)
(Note 19)
Delay time, CAS high to data
Delay time, OE high to data
t
CDD
t
ODD
42
35
0
30
18
5
13
50
20
5
13
15
0
0
10
10
0
0
20
1
20
38
30
13
50
32
25
0
40
20
5
10
50
8
13
0
0
8
8
0
0
13
1
0
50
10
15
0
0
13
13
10
10
0
0
15
1
15
15
ns
ns
Note 14: The timing requirements are assumed
t
T
=2ns.
15: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
16:
t
RCD(max)
is specified as a reference point only. If
t
RCD
is less than
t
RCD(max)
, access time is
t
RAC
. If
t
RCD
is greater than
t
RCD(max
), access time is
controlled exclusively by
t
CAC
or
t
AA
.
17:
t
RAD(max)
is specified as a reference point only. If
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max
), access time is controlled exclusively by
t
AA
.
18:
t
ASC(max)
is specified as a reference point only. If
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
, access time is controlled exclusively by
t
CAC
.
19: Either
t
DZC
or
t
DZO
must be satisfied.
20: Either
t
RDD
or
t
CDD
or
t
ODD
must be satisfied.
21:
t
T
is measured between V
IH(min)
and V
IL(max)
.
20
M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S
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相關(guān)代理商/技術(shù)參數(shù) |
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| M5M44265CTP5 | 制造商:MITS 功能描述:New |
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| M5M44265CTP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M44265CTP-6S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
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