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參數(shù)資料
| 型號： | M5LV-512/160-12YI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 12 ns, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 16/42頁 |
| 文件大?。?/td> | 938K |
| 代理商： | M5LV-512/160-12YI |
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MACH 5 Family
23
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1
-5
-6
-7
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Combinatorial Delay:
tPDi
Internal combinatorial propagation
delay
3.5
4.5
5.5
8.0
10.0
13.0
18.0
ns
tPD
Combinatorial propagation delay
5.5
6.5
7.5
10.0
12.0
15.0
20.0
ns
Registered Delays:
tSS
Synchronous clock setup time
3.0
4.0
5.0
6.0
8.0
10.0
ns
tSA
Asynchronous clock setup time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tHS
Synchronous clock hold time
0.0
ns
tHA
Asynchronous clock hold time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tCOSi
Synchronous clock to internal output
2.5
3.0
4.0
5.0
6.0
8.0
10.0
ns
tCOS
Synchronous clock to output
4.5
5.0
6.0
7.0
8.0
10.0
12.0
ns
tCOAi
Asynchronous clock to internal output
6.0
8.0
10.0
13.0
15.0
18.0
ns
tCOA
Asynchronous clock to output
8.0
10.0
12.0
15.0
17.0
20.0
ns
Latched Delays:
tSAL
Latch setup time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tHAL
Latch hold time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tPDLi
Transparent latch internal
6.0
7.0
8.0
9.0
10.0
ns
tPDL
Propagation delay through transparent
latch
8.0
9.0
10.0
11.0
12.0
ns
tGOAi
Gate to internal output
7.0
8.0
9.0
10.0
11.0
12.0
ns
tGOA
Gate to output
9.0
10.0
11.0
12.0
13.0
14.0
ns
Input Register Delays:
tSIRS
Input register setup time using a
synchronous clock
2.0
3.0
ns
tSIRA
Input register setup time using an
asynchronous clock
0.0
ns
tHIRS
Input register hold time using a
synchronous clock
3.0
4.0
ns
tHIRA
Input register hold time using an
asynchronous clock
6.0
7.0
ns
Input Latch Delays:
tSIL
Input latch setup time
2.0
3.0
ns
tHIL
Input latch hold time
6.0
7.0
ns
tPDILi
Transparent input latch
5.0
5.5
6.0
ns
Output Delays:
tBUF
Output buffer delay
2.0
ns
tSLW
Slow slew rate delay
2.5
ns
tEA
Output enable time
7.5
9.5
10.0
12.0
15.0
20.0
ns
tER
Output disable time
7.5
9.5
10.0
12.0
15.0
20.0
ns
相關PDF資料 |
PDF描述 |
|---|---|
| M50-2020005 | INTERCONNECTION DEVICE |
| M50-3002145 | 42 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, SOCKET |
| M50-3002245 | 44 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, SOCKET |
| M50-3002345 | 46 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, SOCKET |
| M50-3002445 | 48 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER, SOCKET |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M | 功能描述:XLR 連接器 5P ADAPT RECEPTACLE RoHS:否 制造商:Neutrik 標準:Standard XLR 產(chǎn)品類型:Connectors 型式:Female 位置/觸點數(shù)量:3 端接類型:Solder 安裝風格:Cable 方向:Vertical |
| M-5M | 制造商:SMC 功能描述:Fitting manifold 9 port Rc1/8 to M5 |
| M5M1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M5M27C102J15 | 制造商:MITSUBISHI 功能描述:* |
| M5M27C102JK-15 | 制造商:Mitsubishi Electric 功能描述: |
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