- 鎮ㄧ従鍦ㄧ殑浣嶇疆锛�璨疯常IC缍� > PDF鐩寗19688 > M5LV-128/74-5VC (Lattice Semiconductor Corporation)IC CPLD 128MC 74I/O 100TQFP PDF璩囨枡涓嬭級
鍙冩暩璩囨枡
| 鍨嬭櫉锛� | M5LV-128/74-5VC |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋佹暩锛� | 3/42闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CPLD 128MC 74I/O 100TQFP |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | MACH® 5 |
| 鍙法绋嬮鍨嬶細 | 绯荤当鍏у彲绶ㄧ▼ |
| 鏈€澶у欢閬叉檪闁� tpd(1)锛� | 5.5ns |
| 闆诲闆绘簮 - 鍏ч儴锛� | 3 V ~ 3.6 V |
| 瀹忓柈鍏冩暩锛� | 128 |
| 杓稿叆/杓稿嚭鏁革細 | 74 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 100-LQFP |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 100-TQFP锛�14x14锛� |
| 鍖呰锛� | 鎵樼洡 |
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MACH 5 Family
11
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1
Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs. The 5-V
devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other
3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the 3.3-V and 5-V versions have the same
high-speed performance and provide easy-to-use mixed-voltage design capability.
Note:
1.
Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to Application Note titled 鈥淗ot
Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices鈥�.
BUS-FRIENDLY INPUTS AND I/OS
All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two
inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven
logic state. While it is a good design practice to tie unused pins to a known state, the Bus-Friendly input
structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At
power-up, the Bus-Friendly latches are reset to a logic level 鈥�1.鈥� For the circuit diagram, please refer to the
document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
POWER MANAGEMENT
There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power tradeoff can
be tailored for each design. The signal speed paths in the lower-power PAL blocks will be slower than those
in the higher-power PAL blocks. This feature allows speed critical paths to run at maximum frequency while
the rest of the signal paths operate in a lower-power mode. In large designs, there may be several different
speed requirements for different portions of the design.
PROGRAMMABLE SLEW RATE
Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each output can be
individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For
high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less
noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast
slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to
SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a
macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset,
then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be
monotonic and the clock must be inactive until the reset delay time has elapsed.
Table 5. Power Levels
High Speed/High Power
100% Power
Medium High Speed/Medium High Power
67% Power
Medium Low Speed/Medium Low Power
40% Power
Low Speed/Low Power
20% Power
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MIC5206-3.6BMM TR | IC REG LDO 3.6V .15A 8-MSOP |
| VE-20M-CY-F2 | CONVERTER MOD DC/DC 10V 50W |
| VE-20L-CY-F4 | CONVERTER MOD DC/DC 28V 50W |
| VE-20L-CY-F3 | CONVERTER MOD DC/DC 28V 50W |
| 171-050-113R001 | CONN DB50 MALE DIP SOLDER NICKEL |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁� |
鍙冩暩鎻忚堪 |
|---|---|
| M5LV-256/104-10AC | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:Fifth Generation MACH Architecture |
| M5LV-256/104-10AI | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:Fifth Generation MACH Architecture |
| M5LV-256/104-10HC | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:Fifth Generation MACH Architecture |
| M5LV-256/104-10HI | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:Fifth Generation MACH Architecture |
| M5LV-256/104-10VC | 鍔熻兘鎻忚堪:CPLD - 寰╅洔鍙法绋嬮倧杓櫒浠� PROGRAM HI DENSITY CPLD RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜椤炲瀷:EEPROM 澶ч浕姹犳暩閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅傞枔:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
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