參數資料
型號: M5LV-128/104-12VC
廠商: Lattice Semiconductor Corporation
文件頁數: 6/42頁
文件大?。?/td> 0K
描述: IC CPLD 128MC 104I/O 144TQFP
標準包裝: 60
系列: MACH® 5
可編程類型: 系統內可編程
最大延遲時間 tpd(1): 12.0ns
電壓電源 - 內部: 3 V ~ 3.6 V
宏單元數: 128
輸入/輸出數: 104
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
包裝: 托盤
14
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-128/XXX
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
S E G M E N T I N T E R C O N N E C T
CLK0
CLK1
CLK2
CLK3
4
SEGMENT 0
SEGMENT 1
I0, 1
I2, 3
2
20446G-007
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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