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參數(shù)資料
| 型號： | M59MR032D |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 32兆位的2Mb x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 14/49頁 |
| 文件大?。?/td> | 352K |
| 代理商： | M59MR032D |
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M59MR032C, M59MR032D
14/49
Table 13. X-Latency Configuration
Note: 1.
Configuration codes 5 and 6 may be used only in conjunction with configuration bit CR9 set at “1” (one data every 2 clock cycles).
Configuration Code
Input Frequency
100ns
120ns
2
25MHz
20MHz
3
40MHz
30MHz
4
54MHz
40MHz
5
(1)
66MHz
50MHz
6
(1)
–
60MHz
Figure 5. X-Latency Configuration Sequence
AI90113
A16-A20
VALID ADDRESS
K
L
ADQ0-ADQ15
VALID ADDRESS
VALID DATA
VALID DATA
ADQ0-ADQ15
VALID ADDRESS
VALID DATA
ADQ0-ADQ15
VALID ADDRESS
VALID DATA
VALID DATA
VALID DATA
CONFIGURATION CODE 6
CONFIGURATION CODE 3
CONF. CODE 2
– Read mode (CR15).
The device supports an
asynchronous page mode and a synchronous
burst mode. In asynchronous page mode, the
default at power-up, data is internally read and
stored in a buffer of 4 words selected by ADQ0
and ADQ1 address inputs. In synchronous burst
mode, the device latches the starting address
and then outputs a sequence of data which de-
pends on the configuration register settings.
– Bus Invert configuration (CR14).
This regis-
ter bit is used to enable the BINV pin functional-
ity.
BINV
functionality
configuration bits CR14 and CR15 (see Table
12 for configuration bits definition) as shown in
Table 14.
depends
upon
As output pin BINV is active only when enabled
(CR14 = 1) in Read Array burst mode (CR15 = 0).
As input pin BINV is active only when enabled
(CR14 = 1). BINV is ignored when ADQ0-
ADQ15 lines are used as address inputs (ad-
dresses must not be inverted).
Table 14. BINV Configuration Bits
CR15
CR14
BINV
IN
X
OUT
0
Active
0
0
0
0
1
1
0
1
0
1
Active
X
Active
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