參數(shù)資料
型號(hào): M58MR064C
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述: 64兆位4Mb的x16插槽,復(fù)用的I / O,雙行,突發(fā)1.8V電源快閃記憶體
文件頁數(shù): 35/52頁
文件大小: 399K
代理商: M58MR064C
M58MR064C, M58MR064D
40/52
Figure 15. Reset and Power-up AC Waveforms
AI90101
W,
VDD, VDDQ
tPLPH
E, G
tPHWL
tPHEL
tPHGL
tPHWL
tPHEL
tPHGL
tVDHPH
RP
L,
Power-up
Table 31. Reset and Power-up AC Characteristics
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset.
Table 32. Program, Erase Times and Program, Erase Endurance Cycles
(TA = –40 to 85°C; VDD =VDDQ = 1.65V to 2.0V, VPP =VDD unless otherwise specified)
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
3. Same timing value if VPP =12V.
Symbol
Parameter
Test Condition
Min
Unit
tPLPH
(1,2)
RP Pulse Width
100
ns
tPHEL
tPHLL
tPHWL
Reset High to Device Enabled
During Program and Erase
50
s
Other Conditions
30
ns
tVDHPH
(3)
Supply Valid to Reset High
50
s
Parameter
Min
Max (1)
Typ
Typical after
100k W/E Cycles
Unit
Parameter Block (4 K-Word) Erase (Preprogrammed)
2.5
0.5
1
sec
Main Block (32 K-Word) Erase (Preprogrammed)
10
1
3
sec
Bank Erase (Preprogrammed, Bank A)
4
sec
Bank Erase (Preprogrammed, Bank B)
15
sec
Chip Program (2)
40
sec
Chip Program (DPG, VPP = 12V)
(2)
20
sec
Word Program (3)
200
10
s
Double Word Program
200
10
s
Tetra Word Program
200
10
s
Program/Erase Cycles (per Block)
100,000
cycles
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