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參數(shù)資料
| 型號： | M54HC76 |
| 廠商： | 意法半導體 |
| 英文描述： | Dual D Type Flip Flop with Preset and Clear(帶復位和清除的雙D觸發(fā)器) |
| 中文描述： | 雙D型拖鞋與預置和清除（帶復位和清除的雙?觸發(fā)器） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 251K |
| 代理商： | M54HC76 |
M54HC76
M74HC76
October 1992
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
LOWPOWER DISSIPATION
I
CC
= 2
μ
A(MAX.) AT 25
°
C
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS76
B1R
(Plastic Package)
ORDER CODES :
M54HC76F1R
M74HC76B1R
M74HC76M1R
M74HC76C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
f
MAX
= 65 MHz (TYP.) AT V
CC
= 5 V
The M54/74HC76 is a high speedCMOSDUAL J-K
FLIP FLOP fabricated in silicon gate C
2
MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. Depending on with the logic levelat the J
and Kinputs thisdevice changes state on thenega-
tive going transition of the clock pulse. CLEAR and
PRESET are independent of theclock and are ac-
complished by a logic low on the corresponding
input.Allinputs areequipped withprotectioncircuits
against static discharge and transient excess volt-
age.
DESCRIPTION
1/11
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