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參數(shù)資料
| 型號： | M54HC4017F1R |
| 廠商： | 意法半導體 |
| 英文描述： | Low-Voltage, Rail-To-Rail Output CMOS Operational Amplifiers with Shutdown 6-SOT-23 -40 to 125 |
| 中文描述： | 十進制計數(shù)器/分頻器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 258K |
| 代理商： | M54HC4017F1R |
M54HC4017
M74HC4017
October 1992
DECADE COUNTER/DIVIDER
B1R
(Plastic Package)
ORDER CODES :
M54HC4017F1R
M74HC4017B1R
M74HC4017M1R
M74HC4017C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
Q3
DESCRIPTION
.
HIGH SPEED
t
PD
= 21 ns (typ.) ATV
CC
= 5V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
o
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN
4017B
AND
FUNCTION
COMPATIBLEWITH
The M54/74HC4017 is a high speed CMOS DE-
CADE COUNTER/DIVIDER fabricated in silicon
gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low powerconsumption.
The M54/74HC4017 is a 5-stage Johnson counter
with 10 decoded outputs. Each of the decoded out-
puts is normally low and sequentially goes high on
the lowtohigh transition ofthe clockinput.Each out-
put stays high for one clock period of the 10 clock
period cycle. The CARRY output goes low to high
afterOUTPUT 10 goes low,and canbe usedincon-
junction with the CLOCKENABLE to cascade sev-
eral stages.
The CLOCKENABLE input disables counting when
in the high state. A RESET input is also provided
whichwhen takenhigh setsall thedecoded outputs
low.
1/12
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| M54HC4020 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HC4020 14 STAGE BINARY COUNTER HC4040 12 STAGE BINARY COUNTER |
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