參數(shù)資料
型號(hào): M52760
廠商: Mitsubishi Electric Corporation
英文描述: PLL-SPLIT VIF/SIF IC
中文描述: 鎖相環(huán)分割資料表格/應(yīng)力強(qiáng)度因子集成電路
文件頁(yè)數(shù): 5/8頁(yè)
文件大?。?/td> 56K
代理商: M52760
MITSUBISHI ICs (TV)
M52760SP
PLL-SPLIT VIF/SIF IC
5
μ
AFT sensitivity, V
2H
Maximum AFT voltage, V
2L
Minimum AFT
voltage
1. Input SG10 into VIF IN , and set the frequency of SG10 so that
the voltage of AFT output TP2 is 3V. This frequency is f (3).
2. Set the frequency of SG10 so that the AFT output voltage is 2V.
This frequency is f (2)
3. IN the graph, maximum and minimum DC voltage are V
2H
and
V
2L
, respectively.
IM Intermodulation
1. Input SG11 into VIF IN, and measure EQ output TP18A with an
oscilloscope.
2. Adjust AGC filter voltage V8 so that the minimum DC level of the
output waveform is 1.0V.
3. At this time, measure, TP18A with a spectrum analyzer.
The intermodulation is defined as a difference between 1.07MHz
and 4.43MHz frequency components.
LIM Limiting sensitivity
1. Input SG17 (SG21) into SIF input, and measure the 400Hz
component level of AF output TP10.
2. Input SG19 (SG23) into SIF input, and measure the 400Hz
component level of AF output TP10.
3. The input limiting sensitivity is defined as the input level when a
difference between each 400Hz components of audio output
(TP10) is 30dB, as shown below.
AMR AM Rejection
1. Input SG18 into SIF input, and measure the output level of AF
output TP10. This level is VAM.
2. AMR is;
AF S/N
1. Input SG19 into SIF input, and measure the output noise level of
AF output TP1. This level is VN.
2. S/N is;
C
QIF
QIF control
Lower the voltage of V7, and measure the voltage of V7 when the
DC voltage of TP13 begins to change.
THE NOTE IN THE SYSTEM SETUP
M52760SP has 2 power supply pins of Vcc (pin 14) and Vreg.OUT
(pin 17) .
Pin 14 is for AFT output, RF AGC output circuits and 5V regulated
power supply circuit and Pin 17 is for the other circuit blocks.
In case M52760SP is used together with other ICs like VIF
operating at more than 5V, the same supply voltage as that of
connected ICs is applied to V
CC
and Vreg.Out is opened. The other
circuit blocks, connected to Vreg.OUT are powered by internal 5V
regulated power supply.
In case the connecting ICs are operated at 5V, 5V is supplied to
both V
CC
and Vreg.OUT.
LOGIC TABLE
f (3)
f (2)
f (MHz)
V
2L
V
2H
TP2
Voltage
3V
2V
μ =
1000 (mV)
f (2) - f (3) (kHz)(mV/kHz)
30dB
(dB
μ
)
(mVrms)
Audio output while
SG17 (SG21) is input
Audio output while
SG19 (SG23) is input
Audio output
SIF input
AF
AFT
10k “H”
20k “H”
20k “L”
20k “H”
20k “L”
NTSC
DEFEAT
NORMAL
DEFEAT
NORMAL
10k “L”
PAL
AMR=20log
VoAF (mVr.m.s)
VAM (mVr.m.s)
(dB)
S/N=20log
VoAF (mVr.m.s)
VN (mVr.m.s)
(dB)
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