- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗19583 > M5-320/160-7YI (Lattice Semiconductor Corporation)IC CPLD ISP 320MC 160IO 208PQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | M5-320/160-7YI |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 19/42闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CPLD ISP 320MC 160IO 208PQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 24 |
| 绯诲垪锛� | MACH® 5 |
| 鍙法绋嬮鍨嬶細 | 绯荤当(t菕ng)鍏�(n猫i)鍙法绋� |
| 鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� | 7.5ns |
| 闆诲闆绘簮 - 鍏�(n猫i)閮細 | 4.5 V ~ 5.5 V |
| 瀹忓柈鍏冩暩(sh霉)锛� | 320 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 160 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 208-BFQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 208-PQFP锛�28x28锛� |
| 鍖呰锛� | 鎵樼洡 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�鐣�(d膩ng)鍓嶇19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�
26
MACH 5 Family
1.
These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where these parameters may be affected.
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequency. The
selected 鈥渢ypical鈥� pattern is a 16-bit up-down counter. This pattern fills the device and exercises every
macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are
optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is
placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed
in a common PAL block and set to lowest power. For a more detailed discussion about MACH 5 power
consumption, refer to the application note entitled MACH 5 Power in the Application Notes section on the
Lattice Data Book CD-ROM or Lattice web site.
ICC CURVES AT HIGH /LOW POWER MODES
CAPACITANCE1
Parameter Symbol
Parameter
Description
Test conditions
Typ
Unit
CIN
I/CLK pin
VIN =2.0 V
3.3 V or 5 V, 25 C, 1 MHz
12
pF
CI/O
I/O pin
VOUT =2.0 V
3.3 V or 5 V, 25 C, 1 MHz
10
pF
700
600
500
400
300
200
100
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
VCC = 5 V or 3.3 V, TA = 25 C
M5(LV)-512 high power
M5(LV)-384 high power
M5(LV)-320 high power
M5-256/1 and
M5LV-25 high power
M5-128/1 and M5LV-128 high power
M5(LV)-384 low power
M5(LV)-320 low power
M5-256/1 and M5LV-256 low power
M5-128/1 and M5LV-128 low power
I CC
(mA)
Frequency (MHz)
20446G-048
Figure 8. ICC Curves at High/Low Power Modes
M5-192/1 high power
M5-192/1 low power
M5(LV)-512 low power
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| M5-320/160-6YC | IC CPLD ISP 320MC 160IO 208PQFP |
| GSM06DTMD-S189 | CONN EDGECARD 12POS R/A .156 SLD |
| MIC5256-2.8BM5 TR | IC REG LDO 2.8V .15A SOT23-5 |
| LC51024VG-75F484I | IC XPLD 1024MC 7.5NS 484FPBGA |
| EPM7032STI44-7N | IC MAX 7000 CPLD 32 44-TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| M53-20171HLF | 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors |
| M53-20171VLF | 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors |
| M53-20190HLF | 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors |
| M53-20190VLF | 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors |
| M53-20350HLF | 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
