1. See 鈥淢ACH Switching Test Circuits鈥� documentation on the Lattice Data Book CD-ROM or Lattice web site. 2.
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� M5-320/160-6YC
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 18/42闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CPLD ISP 320MC 160IO 208PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� MACH® 5
鍙法绋嬮鍨嬶細 绯荤当(t菕ng)鍏�(n猫i)鍙法绋�
鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� 6.5ns
闆诲闆绘簮 - 鍏�(n猫i)閮細 4.75 V ~ 5.25 V
瀹忓柈鍏冩暩(sh霉)锛� 320
杓稿叆/杓稿嚭鏁�(sh霉)锛� 160
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
鍖呰锛� 鎵樼洡
MACH 5 Family
25
Notes:
1.
See 鈥淢ACH Switching Test Circuits鈥� documentation on the Lattice Data Book CD-ROM or Lattice web site.
2.
Numbers in parentheses are for M5-128, M5-192, M5-256.
3.
If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (fMAX/2).
Frequency:
fMAX
External feedback, PAL block level. Min
of 1/(tWLS + tWHS) or 1/(tSS + tCOS)
133
125
100
83.3
71.4
55.6
45.5
MHz
Internal feedback, PAL block level. Min
of 1/(tWLS + tWHS) or 1/(tSS +tCOSi)
182
167
125
100
83.3
62.5
50.0
MHz
No feedback PAL block level. Min of
1/(tWLS + tWHS) or 1/(tSS + tHS)
200
167
125
100
83.3
MHz
fMAXA
External feedback, PAL block level. Min
of 1/(tWLA + tWHA) or 1/(tSA + tCOA)
91
71.4
58.8
47.6
41.7
35.7
MHz
Internal feedback, PAL block level. Min
of 1/(tWLA + tWHA) or 1/(tSA +tCOAi)
111
83.3
66.7
52.6
45.5
38.5
MHz
No feedback, PAL block level. Min of
1/(tWLA + tWHA) or 1/(tSA + tHA)
167
125
100
83.3
71.4
62.5
MHz
fMAXI
Maximum input register frequency
1/(tSIRS+tHIRS) or 1/(2 x tWICW)
167
125
100
83.3
71.4
62.5
MHz
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-6
-7
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
GSM06DTMD-S189 CONN EDGECARD 12POS R/A .156 SLD
MIC5256-2.8BM5 TR IC REG LDO 2.8V .15A SOT23-5
LC51024VG-75F484I IC XPLD 1024MC 7.5NS 484FPBGA
EPM7032STI44-7N IC MAX 7000 CPLD 32 44-TQFP
AGM22DRST-S664 CONN EDGECARD 44POS DIP .156 SLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
M53-20171HLF 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors
M53-20171VLF 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors
M53-20190HLF 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors
M53-20190VLF 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors
M53-20350HLF 鍒堕€犲晢:BITECH 鍒堕€犲晢鍏ㄧū:Bi technologies 鍔熻兘鎻忚堪:High Power Low Cost Inductors