參數(shù)資料
型號： M4A5-96/48-7VI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High Performance E 2 CMOS In-System Programmable Logic
中文描述： EE PLD, 7.5 ns, PQFP100
封裝： TQFP-100
文件頁數(shù)： 10/62頁
文件大?。?/td> 1078K
代理商： M4A5-96/48-7VI
18
ispMACH 4A Family
Input Switch Matrix
The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix.
Without the input switch matrix, each input and feedback signal has only one way to enter the central switch
matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix.
To
Central
Switch
Matrix
From
Macrocell
2
From Input Cell
Direct
From
Macrocell
1
Registered/Latched
17466G-002
17466G-003
Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell
Ratio - Input Switch Matrix
Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell
Ratio - Input Switch Matrix
To
Central
Switch
Matrix
From
Macrocell
From
I/O
Pin
相關(guān)PDF資料
PDF描述
M4A3-128/64-12VI High Performance E 2 CMOS In-System Programmable Logic
M4A3-128/64-12YI High Performance E 2 CMOS In-System Programmable Logic
M4A3-128/64-55CAC High Performance E 2 CMOS In-System Programmable Logic
M4A3-128/64-55VC High Performance E 2 CMOS In-System Programmable Logic
M4A3-128/64-55YC High Performance E 2 CMOS In-System Programmable Logic
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