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    參數(shù)資料
    

    


    


    
型號(hào)：
M4A3-256/128-55FANC

    

    
廠商：
Lattice Semiconductor Corporation

    

    
文件頁(yè)數(shù)：
13/62頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC CPLD ISP 4A 256MC 256FPBGA

    

    
標(biāo)準(zhǔn)包裝：
90

    

    
系列：
ispMACH® 4A

    

    
可編程類(lèi)型：
系統(tǒng)內(nèi)可編程
    		

    

    
最大延遲時(shí)間 tpd(1)：
5.5ns
    		

    

    
電壓電源 - 內(nèi)部：
3 V ~ 3.6 V
    		

    

    
宏單元數(shù)：
256
    		

    

    
輸入/輸出數(shù)：
128
    		

    

    
工作溫度：
0°C ~ 70°C
    		

    

    
安裝類(lèi)型：
表面貼裝
    		

    

    
封裝/外殼：
256-BGA
    		

    

    
供應(yīng)商設(shè)備封裝：
256-FPBGA（17x17）
    		

    

    
包裝：
托盤(pán)
    		

    

    

    

	
    
    
    

    
    
	
    20
    ispMACH 4A Family
    ispMACH 4A TIMING MODEL
    The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH
    4A device, and at the same time, be easy to understand. This model accurately describes all combinatorial
    and registered paths through the device, making a distinction between internal feedback and external
    feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having
    to go through the output buffer. The input register specifications are also reported as internal feedback.
    When a signal is fed back into the switch matrix after having gone through the output buffer, it is using
    external feedback.
    The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the
    I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is
    followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For
    example, tPD = tPDi + tBUF. A diagram representing the modularized ispMACH 4A timing model is shown
    in Figure 15. Refer to the application note entitled MACH 4 Timing and High Speed Design for a more detailed
    discussion about the timing parameters.
    SPEEDLOCKING FOR GUARANTEED FIXED TIMING
    The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual macrocell with
    the assistance of an XOR gate without incurring additional timing delays.
    The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of
    the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms
    expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs
    easy access to the performance required in today’s designs.
    (External Feedback)
    (Internal Feedback)
    INPUT REG/
    INPUT LATCH
    tSIRS
    tHIRS
    tSIL
    tHIL
    tSIRZ
    tHIRZ
    tSILZ
    tHILZ
    tPDILi
    tICOSi
    tIGOSi
    tPDILZi
    Q
    tSS(T)
    tSA(T)
    tH(S/A)
    tS(S/A)L
    tH(S/A)L
    tSRR
    tPDi
    tPDLi
    tCO(S/A)i
    tGO(S/A)i
    tSRi
    COMB/DFF/TFF/
    LATCH/SR*/JK*
    S/R
    IN
    BLK CLK
    OUT
    tPL
    tBUF
    tEA
    tER
    tSLW
    Q
    Central
    Switch
    Matrix
    *emulated
    17466G-025
    Figure 15. ispMACH 4A Timing Model
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
MIC5206-4.0BMM TR
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ISPLSI 2096E-180LT128
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MIC5206-4.0BMM
IC REG LDO 4V .15A 8-MSOP

    

    
MIC5206-3.8BMM TR
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VE-20N-CY-F4
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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
M4A3-32/32-10JC
功能描述:CPLD - 復(fù)雜可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
M4A3-32/32-10JI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
M4A3-32/32-10JNC
功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
M4A3-32/32-10JNI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
M4A3-32/32-10VC
功能描述:CPLD - 復(fù)雜可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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