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參數(shù)資料
| 型號： | M48Z512AY-70PM1 |
| 廠商： | 意法半導體 |
| 英文描述： | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| 中文描述： | 4兆位的SRAM 512KB的x8 ZEROPOWER |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 101K |
| 代理商： | M48Z512AY-70PM1 |
1/17
March 2000
M48Z512A
M48Z512AY
4 Mbit (512Kb x8) ZEROPOWER
SRAM
I
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
I
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
I
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
I
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
I
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z512A: 4.50V
≤
V
PFD
≤
4.75V
– M48Z512AY: 4.20V
≤
V
PFD
≤
4.50V
I
BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
I
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 512K x 8 SRAMs
I
SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
I
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
I
SNAPHAT
HOUSING (BATTERY) IS
REPLACEABLE
Figure 1. Logic Diagram
AI02043
19
A0-A18
W
DQ0-DQ7
VCC
M48Z512A
M48Z512AY
G
VSS
8
E
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
32
1
32
1
SOH28
Surface Mount Chip Set Solution (CS)
SNAPHAT (SH)
Battery
PMDIP32 (PM)
Module
TSOP II 32
(10 x 20mm)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z512AY-70PM1E | 制造商:STMicroelectronics 功能描述: |
| M48Z512AY-70PM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER? SRAM |
| M48Z512AY-70PM9 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z512AY-7-PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER SRAM |
| M48Z512AY-7-PM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER SRAM |
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