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參數(shù)資料
| 型號： | M48T59V-70MH6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 27/29頁 |
| 文件大?。?/td> | 440K |
| 代理商： | M48T59V-70MH6 |
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M48T59, M48T59Y, M48T59V*
READ Mode
The M48T59/Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 13 ad-
dress inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
Figure 7. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V, 4.75 to 5.5V, or 3.0 to 3.6V (except
where noted).
Symbol
Parameter(1)
M48T59/Y/V
Unit
–70
Min
Max
tAVAV
READ Cycle Time
70
ns
tAVQV
(2)
Address Valid to Output Valid
70
ns
tELQV
(2)
Chip Enable Low to Output Valid
70
ns
tGLQV
(2)
Output Enable Low to Output Valid
35
ns
tELQX
(3)
Chip Enable Low to Output Transition
5
ns
tGLQX
(3)
Output Enable Low to Output Transition
5
ns
tEHQZ
(3)
Chip Enable High to Output Hi-Z
25
ns
tGHQZ
(3)
Output Enable High to Output Hi-Z
25
ns
tAXQX
(2)
Address Transition to Output Transition
10
ns
AI01385
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A12
E
G
DQ0-DQ7
VALID
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48T59V-70MH6E | REAL TIME CLOCK, PDSO28 |
| M48T59V-70MH6TR | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M48T59Y-70MH6F | REAL TIME CLOCK, PDSO28 |
| M48T86MH1E | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| M4T32-BR12SH1 | 1 TIMER(S), REAL TIME CLOCK, DSS4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T59V-70MH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| M48T59V-70PC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70PC1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70PC1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 64 Kbit (8 Kbit x 8) TIMEKEEPER? SRAM |
| M48T59V-70PC1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Kbit 8Kb x8 TIMEKEEPER SRAM |
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