參數(shù)資料
型號(hào)： M48T559YMH1
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO28
封裝： 0.330 INCH, PLASTIC, SOH-28
文件頁(yè)數(shù)： 5/26頁(yè)
文件大?。?/td> 364K
代理商： M48T559YMH1
13/26
M48T559Y
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop Bit (ST, D7 of 1FF9h) is '0,' the Frequency
Test Bit (FT, D6 of 1FFCh) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of 1FF6h) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 1FF7h) is '1'
or the Watchdog Register (1FF7h = 0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature.
For
example,
a
reading
of
512.010124 Hz would indicate a +20 ppm oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequen-
cy. The FT Bit is cleared on power-down.
For more information on calibration, see the Appli-
cation Note AN934, “TIMEKEEPER Calibration”.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10k
resistor is recommended in order to
control the rise time.
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight-bit Watchdog Register (Ad-
dress 1FF7h). The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1-
RB0) select the resolution, where 00 = 1/16 sec-
ond, 01 = 1/4 second, 10 = 1 second, and 11 = 4
seconds. The amount of time-out is then deter-
mined to be the multiplication of the five-bit multi-
plier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3 x
1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T559Y sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 1FF0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a '0,' the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a '1,' the watchdog will
output a negative pulse on the RST pin for a dura-
tion of 40ms to 200ms. The Watchdog register,
FT, AFE, and ABE bits will reset to a '0' at the end
of a watchdog time-out when the WDS Bit is set to
a '1.'
The watchdog timer can be reset by two methods:
– a transition (high-to-low or low-to-high) can be
applied to the Watchdog input pin (WDI); or
– the microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over. The WDI pin contains a pull-down
resistor and therefore must be grounded if not
used.
The watchdog timer will be reset on each transition
(edge) seen by the WDI pin. In order to perform a
software reset of the Watchdog timer, the original
time-out period can be written into the Watchdog
Register, effectively restarting the count-down cy-
cle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (D7; Address 1FF0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
Power-on Reset
The M48T559Y continuously monitors VCC. When
VCC falls to the power fail detect trip point, the RST
pulls low (open drain) and remains low on power-
up
for
40ms
to
200ms
after
VCC passes
VPFD (max). An external pull-up resistor to VCC is
required (1K
resistor is recommended). The re-
set pulse remains active with VCC at VSS.
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