參數(shù)資料
型號(hào): M48T37V-70MH6E
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, PDSO44
封裝: 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOIC-44
文件頁(yè)數(shù): 10/29頁(yè)
文件大?。?/td> 276K
代理商: M48T37V-70MH6E
Clock operations
M48T37Y, M48T37V
which require extensive durations in the battery back-up mode should be powered-up
periodically (at least once every few months) in order for this technique to be beneficial.
Additionally, if a battery low is indicated, data integrity should be verified upon power-up via
a checksum or other technique.
3.10
Initial power-on defaults
Upon application of power to the device, the following register bits are set to a '0' state:
WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT (see Table 7).
Table 7.
Default values
3.11
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if
capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in
Figure 9) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Condition
W
R
FT
AFE
ABE
WATCHDOG
Register(1)
1.
WDS, BMB0-BMB4, RBO, RB1.
Initial Power-up
(Battery Attach for SNAPHAT)(2)
2.
State of other control bits undefined.
00
0
Subsequent Power-up / RESET(3)
3.
State of other control bits remains unchanged.
00
0
Power-down(4)
4.
Assuming these bits set to '1' prior to power-down.
00
01
1
0
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