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參數(shù)資料
| 型號(hào)： | M48T35Y-70MH1E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, SNAPHAT, ROHS COMPLIANT, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大小： | 256K |
| 代理商： | M48T35Y-70MH1E |
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M48T35 M48T35Y
Operation modes
2.3
Data retention mode
With valid VCC applied, the M48T35/Y operates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care” (see Figure 12 on
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T35/Y may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35/Y for an accumulated period of at least 7 years when VCC is less than VSO. As
system power returns and VCC rises above VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min)
plus trec (min). E should be kept high as VCC rises past VPFD (min) to prevent inadvertent
WRITE cycles prior to processor stabilization. Normal RAM operation can resume trec after
VCC exceeds VPFD (max).
For more information on battery storage life refer to the application note AN1012.
tWLWH
WRITE enable pulse width
50
ns
tELEH
Chip enable low to chip enable high
55
ns
tWHAX
WRITE enable high to address transition
0
ns
tEHAX
Chip enable high to address transition
0
ns
tDVWH
Input valid to WRITE enable high
30
ns
tDVEH
Input valid to chip enable high
30
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ
(2)(3)
WRITE enable low to output Hi-Z
25
ns
tAVWH
Address valid to WRITE enable high
60
ns
tAVEH
Address valid to chip enable high
60
ns
tWHQX
WRITE enable high to output transition
5
ns
1.
Valid for ambient operating temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
2.
CL = 5 pF.
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Table 4.
Write mode AC characteristics (continued)
Symbol
Parameter(1)
M48T35/Y
Unit
Min
Max
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T35Y-70MH1F | 功能描述:實(shí)時(shí)時(shí)鐘 256K (32Kx8) 70ns RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| M48T35Y-70MH1F-CUT TAPE | 制造商:ST 功能描述:M48T35Y Series 256 Kb (32 K x 8) 5.5 V 70 ns Timekeeper?SRAM - SOH-28 |
| M48T35Y-70MH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35Y-70MH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| M48T35Y-70MH6E | 功能描述:實(shí)時(shí)時(shí)鐘 256K (32Kx8) 70ns RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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