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參數(shù)資料
| 型號： | M48T212AMH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3.3V TIMEKEEPER CONTROLLER |
| 中文描述： | 3.3計(jì)時(shí)控制器 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | M48T212AMH |
1/20
PRELIMINARY DATA
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M48T212A
3.3V TIMEKEEPER
CONTROLLER
I
CONVERTS LOW POWER SRAM into
NVRAMs
I
YEAR 2000 COMPLIANT (4-Digit Year)
I
USES SUPER CAPACITOR or LITHIUM
BATTERY (User Supplied)
I
BATTERY LOW FLAG
I
INTEGRATED REAL TIME CLOCK,
POWER-FAIL CONTROL CIRCUIT
I
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
I
WATCHDOG TIMER
I
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48T212A: 2.7V
≤
V
PFD
≤
3.0V
I
MICROPROCESSOR POWER-ON RESET
I
PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACKED-UP MODE
DESCRIPTION
The M48T212A is a self-contained device that in-
cludes a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.
A built-in 32.768 kHz oscillator (external crystal
controlled) is used for the clock/calendar function.
Access to all TIMEKEEPER functions and the ex-
ternal RAM is the same as conventional byte-wide
SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Control, Calibration, Alarm, Watchdog,
and Flags. Externally attached static RAMs are
controlled by the M48T212A via the E1
CON
and
E2
CON
signals (see Table 4).
Automatic backup and write protection for an ex-
ternal SRAM is provided through V
OUT
, E1
CON
and E2
CON
pins. (Users are urged to insure that
voltage specifications, for both the controller chip
and external SRAM chosen, are similar).
Figure 1. Logic Diagram
AI03047
4
A0-A3
A
DQ0-DQ7
VCC
M48T212A
G
VSS
8
EX
E2CON
E1CON
W
RSTIN2
RSTIN1
RST
IRQ/FT
VOUT
WDI
E
VCAP
X0
XI
VCCSW
VBAT–
SOH44 (MH)
44
1
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